A review of soft errors and the low α-solder bumping process in 3-D packaging technology

DH Jung, A Sharma, JP Jung - Journal of Materials Science, 2018 - Springer
This study reviews soft errors in modern electronic assemblies, through silicon via (TSV),
and low α-solder bumping techniques for 3-D microelectronic packaging. The TSV …

Transient cooling and heating effects in holey silicon-based lateral thermoelectric devices for hot spot thermal management

Z Ren, JC Kim, J Lee - IEEE Transactions on Components …, 2021 - ieeexplore.ieee.org
Lateral thermoelectric devices, where the Peltier cooling and heating occur in a lateral
direction, have shown promise for thermal management of on-chip hot spots, and because …

Air-gap through-silicon vias

C Huang, Q Chen, Z Wang - IEEE electron device letters, 2013 - ieeexplore.ieee.org
This letter reports for the first time the fabrication and characterization of through-silicon vias
(TSVs) using air-gap insulators to enable high-performance 3-D integration. To address the …

Thermal and electrical properties of BCB-liner through-silicon vias

C Huang, L Pan, R Liu, Z Wang - IEEE Transactions on …, 2014 - ieeexplore.ieee.org
Through-silicon vias (TSVs) using benzocyclobutene (BCB)-liners as the insulator have the
potential for reducing the TSV capacitances and the thermal expansion stresses. This paper …

Study of vacuum-assisted spin coating of polymer liner for high-aspect-ratio through-silicon-via applications

Y Yan, Y Ding, T Fukushima, KW Lee… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This paper provides a new approach for the formation of polymer liner for low-k high-aspect-
ratio through-silicon-vias involved in via-last backside-via 3-D integration applications. The …

Formation of polymer insulation layer (liner) on through silicon vias (TSV) with high aspect ratio over 5: 1 by direct spin coating

L Li, G Zhang, CC Tuan, KS Moon… - 2016 IEEE 66th …, 2016 - ieeexplore.ieee.org
Through silicon vias (TSV) are the enabling components in the emerging 2.5 D and 3D
integration microelectronic packaging. The insulation layer, ie the liner, plays the key role in …

Low capacitance and highly reliable blind through-silicon-vias (TSVs) with vacuum-assisted spin coating of polyimide dielectric liners

YY Yan, M Xiong, B Liu, YT Ding, ZM Chen - Science China Technological …, 2016 - Springer
Low-k and high aspect ratio blind through-silicon-vias (TSVs) to be applied in “via-
last/backside via” 3-D integration paradigm were fabricated with polyimide dielectric liners …

High-frequency characterization of through-silicon-Vias with benzocyclobutene liners

K Wu, Z Wang - IEEE Transactions on Components, Packaging …, 2017 - ieeexplore.ieee.org
This paper presents design, fabrication, and high-frequency characterization of through-
silicon-vias (TSVs) with benzocyclobutene (BCB) as the dielectric liner to exploit its low …

Thermal stresses of TSVs with silicon post conductors and polymer insulators

Q Ma, K Wu, Z Wang - IEEE Transactions on Components …, 2016 - ieeexplore.ieee.org
Due to the advantages of ease of fabrication, low cost, and potential high reliability, through-
silicon-vias (TSVs) using low-resistivity silicon posts as conductors and circular polymer …

Thermal and electrical reliability tests of air-gap through-silicon vias

C Huang, R Liu, Z Wang - IEEE Transactions on Device and …, 2014 - ieeexplore.ieee.org
Through-silicon vias (TSVs) with air gaps as the isolators have been developed to reduce
the TSV capacitance and to solve the reliability problems associated with thermomechanical …