This brief presents an odd phase Bang-Bang phase detector-based CDR architecture that
has a unique property that the clock phases sampling the data automatically become …

An energy-efficient forwarded-clock transmitter that offers a scalable pre-emphasis
equalization and output voltage swing is presented. A resistive-feedback inverter-based …

This brief presents a power-and area-efficient forwarded-clock (FC) receiver with a delay-
locked loop (DLL)-based self-tracking loop for unmatched memory interfaces. In the …

This chapter is devoted to the development of means in I/O blocks that will allow to increase
the frequency of the transmitted signal and to level the distorted signal. Effective approaches …

It is well known that timing jitter can degrade the bit error rate of receivers that recover the
clock from input data. However, timing jitter can also result in an indefinite increase in the …

It is well known that timing jitter can degrade the bit error rate (BER) of receivers that recover
clock information from the input data. In this paper, we show that timing jitter can also result …

To cope with problems caused by the high-speed operation of the dynamic random access
memory (DRAM) interface, several approaches are proposed that are focused on the clock …

This thesis proposes a low-cost high-efficiency source-synchronous interface for high-speed
inter-chip communication. The interface is composed of LVDS transceivers as external I/O …

Innovative injection-locking techniques for a high-speed serial link are proposed in both
transmitter and receiver. Superior jitter performance is achieved using directly injecting the …