Lockstep dual-core ARM A9: Implementation and resilience analysis under heavy ion-induced soft errors

ÁB de Oliveira, GS Rodrigues… - … on Nuclear Science, 2018 - ieeexplore.ieee.org
This paper presents a dual-core lockstep (DCLS) implementation to protect hard-core
processors against radiation-induced soft errors. The proposed DCLS is applied to an …

Radiation testing of a multiprocessor macrosynchronized lockstep architecture with FreeRTOS

PM Aviles, A Lindoso, JA Belloch… - … on Nuclear Science, 2021 - ieeexplore.ieee.org
Nowadays, high-performance microprocessors are demanded in many fields, including
those with high-reliability requirements. Commercial microprocessors present a good …

Analyzing lockstep dual-core ARM cortex-A9 soft error mitigation in FreeRTOS applications

ÁB de Oliveira, GS Rodrigues… - Proceedings of the 30th …, 2017 - dl.acm.org
This paper evaluates the efficiency and performance impact of a dual-core lockstep as a
method for fault-tolerance running on top of FreeRTOS applications. The method was …

Fault-tolerant nanosatellite computing on a budget

CM Fuchs, NM Murillo, A Plaat… - 2018 18th European …, 2018 - ieeexplore.ieee.org
We present an on-board computer architecture designed for small satellites (<; 50kg), which
exploits software-fault-tolerance to achieve strong fault coverage with commodity hardware …

[HTML][HTML] System-on-chip single event effect hardening design and validation using proton irradiation

W Yang, Y Li, G Guo, C He, L Wu - Nuclear Engineering and Technology, 2023 - Elsevier
A multi-layer design is applied to mitigate single event effect (SEE) in a 28 nm System-on-
Chip (SoC). It depends on asymmetric multiprocessing (AMP), redundancy and system …

An Efficient Fault-Tolerant Instruction Decoder for RISC-V Based Dual-Core Soft-Processors

S Shukla, M Azam, KC Ray - IEEE Transactions on Circuits …, 2023 - ieeexplore.ieee.org
In the modern era, FPGA-based soft-core processors have gained much attention in space
applications due to their flexibility and ease of integration. In such applications, radiation can …

[PDF][PDF] Fault-tolerant satellite computing with modern semiconductors

CM Fuchs - American Conference on …, 2010 - scholarlypublications …
[107] MD Berg, HS Kim, AM Phan, CM Seidleck, KA LaBel, JA Pellish, and MJ Campola,“The
effects of race conditions when implementing singlesource redundant clock trees in triple …

Fault tolerant soft-core processor architecture based on temporal redundancy

PRC Villa, R Travessini, RC Goerl, FL Vargas… - Journal of Electronic …, 2019 - Springer
Embedded soft-core processors are becoming the usual solution to deal with network and
data communications inside FPGAs. However, when developing space-based applications …

Systems and Debugging Supports for Hardware Designs

J Ma - 2024 - deepblue.lib.umich.edu
The development and deployment of hardware and software have traditionally been quite
distinct. Software benefits from an agile development cycle, aided by a wide array of …

Multi-threaded mitigation of radiation-induced soft errors in bare-metal embedded systems

A Serrano-Cases, F Restrepo-Calle… - Journal of Electronic …, 2020 - Springer
This article presents a software protection technique against radiation-induced faults which
is based on a multi-threaded strategy. Data triplication and instructions flow duplication or …