A critical review on performance, reliability, and fabrication challenges in nanosheet FET for future analog/digital IC applications

S Valasa, S Tayal, LR Thoutam, J Ajayan… - Micro and …, 2022 - Elsevier
This article critically reviews the fabrication challenges, emerging materials (wafer, high-k
oxide, gate metal, channel materials), dimensional influences, thermal effects, growth …

A device-to-system perspective regarding self-heating enhanced hot carrier degradation in modern field-effect transistors: A topical review

MA Alam, BK Mahajan, YP Chen, W Ahn… - … on Electron Devices, 2019 - ieeexplore.ieee.org
As foreseen by Keyes in the late 1960s, the self-heating effect has emerged as an important
concern for device performance, output power density, run-time variability, and reliability of …

Layout design correlated with self-heating effect in stacked nanosheet transistors

L Cai, W Chen, G Du, X Zhang… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
With technology node scaling down to 5 nm, the narrow device geometry confines the
material thermal conductivity and further aggravates the self-heating effect in gate-all-around …

Security closure of physical layouts ICCAD special session paper

J Knechtel, J Gopinath, J Bhandari… - 2021 IEEE/ACM …, 2021 - ieeexplore.ieee.org
Computer-aided design (CAD) tools traditionally optimize for power, performance, and area
(PPA). However, given a vast number of hardware security threats, we call for secure-by …

Heterogeneous and monolithic 3D integration technology for mixed-signal ICs

J Jeong, DM Geum, SH Kim - Electronics, 2022 - mdpi.com
For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display,
etc.) which require high-performance, small form factors, and low power consumption …

A vertical combo spacer to optimize electrothermal characteristics of 7-nm nanosheet gate-all-around transistor

R Liu, X Li, Y Sun, Y Shi - IEEE Transactions on Electron …, 2020 - ieeexplore.ieee.org
In this article, the impact of self-heating effect (SHE) on nanosheet gate-all-around (GAA)
transistor with a vertical combo spacer and different underlap/overlap channels is studied by …

Reliability modeling and analysis of hot-carrier degradation in multiple-fin SOI n-channel FinFETs with self-heating

A Gupta, C Gupta, RA Vega, TB Hook… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
A comprehensive study on hot-carrier degradation (HCD) mechanisms in 14 nm silicon-on-
insulator (SOI) n-channel FinFETs is presented. The impact of high-frequency AC stress bias …

Integrated modeling of self-heating of confined geometry (FinFET, NWFET, and NSHFET) transistors and its implications for the reliability of sub-20 nm modern …

W Ahn, SH Shin, C Jiang, H Jiang, MA Wahab… - Microelectronics …, 2018 - Elsevier
The evolution of transistor topology from planar to confined geometry transistors (ie, FinFET,
Nanowire FET, Nanosheet FET) has met the desired performance specification of sub-20 nm …

BOX engineering to mitigate negative differential resistance in MFIS negative capacitance FDSOI FET: an analog perspective

N Chauhan, N Bagga, S Banchhor, C Garg… - …, 2021 - iopscience.iop.org
Till date, the existing understanding of negative differential resistance (NDR) is obtained
from metal-ferro–metal–insulator–semiconductor (MFMIS) FET, and it has been utilized for …

Investigation of self-heating effects in gate-all-around MOSFETs with vertically stacked multiple silicon nanowire channels

JY Park, BH Lee, KS Chang, DU Kim… - … on Electron Devices, 2017 - ieeexplore.ieee.org
The self-heating effects (SHEs) in gate-all-around (GAA) MOSFETs with vertically stacked
silicon nanowire (SiNW) channels are investigated. Direct observations using thermal …