One-IPC high-level simulation of microthreaded many-core architectures
I Uddin - The International Journal of High Performance …, 2017 - journals.sagepub.com
The microthreaded many-core architecture is comprised of multiple clusters of fine-grained
multi-threaded cores. The management of concurrency is supported in the instruction set …
multi-threaded cores. The management of concurrency is supported in the instruction set …
High-level simulation of concurrency operations in microthreaded many-core architectures
I Uddin - GSTF Journal on Computing (JoC), 2015 - Springer
Computer architects are always interested in analyzing the complex interactions amongst
the dynamically allocated resources. Generally a detailed simulator with a cycle-accurate …
the dynamically allocated resources. Generally a detailed simulator with a cycle-accurate …
Apple-CORE: Microgrids of SVP Cores--Flexible, General-Purpose, Fine-Grained Hardware Concurrency Management
To harness the potential of CMPs for scalable, energy-efficient performance in general-
purpose computers, the Apple-CORE project has co-designed a general machine model …
purpose computers, the Apple-CORE project has co-designed a general machine model …
MGSim—A simulation environment for multi-core research and education
This article presents MGSim 1, an open source discrete event simulator for on-chip
hardware components developed at the University of Amsterdam. MGSim is used as …
hardware components developed at the University of Amsterdam. MGSim is used as …
MGSim-Simulation tools for multi-core processor architectures
MGSim is an open source discrete event simulator for on-chip hardware components,
developed at the University of Amsterdam. It is intended to be a research and teaching …
developed at the University of Amsterdam. It is intended to be a research and teaching …
[HTML][HTML] Multiple levels of abstraction in the simulation of microthreaded many-core architectures
I Uddin - Open Journal of Modelling and Simulation, 2015 - scirp.org
Simulators are generally used during the design of computer architectures. Typically,
different simulators with different levels of complexity, speed and accuracy are used …
different simulators with different levels of complexity, speed and accuracy are used …
Cache-based high-level simulation of microthreaded many-core architectures
The accuracy of simulated cycles in high-level simulators is generally less than the accuracy
in detailed simulators for a single-core systems, because high-level simulators simulate the …
in detailed simulators for a single-core systems, because high-level simulators simulate the …
Apple-CORE: harnessing general-purpose many-cores with hardware concurrency management
To harness the potential of CMPs for scalable, energy-efficient performance in general-
purpose computers, the Apple-CORE project has co-designed a general machine model …
purpose computers, the Apple-CORE project has co-designed a general machine model …
Signature-based high-level simulation of microthreaded many-core architectures
The simulation of fine-grained latency tolerance based on the dynamic state of the system in
high-level simulation of many-core systems is a challenging simulation problem. We have …
high-level simulation of many-core systems is a challenging simulation problem. We have …
SL: a" quick and dirty" but working intermediate language for SVP systems
R Poss - arXiv preprint arXiv:1208.4572, 2012 - arxiv.org
The CSA group at the University of Amsterdam has developed SVP, a framework to manage
and program many-core and hardware multithreaded processors. In this article, we …
and program many-core and hardware multithreaded processors. In this article, we …