[图书][B] Efficient microarchitecture for network-on-chip routers

DU Becker - 2012 - search.proquest.com
Continuing advances in semiconductor technology, coupled with an increasing concern for
energy efficiency, have led to an industry-wide shift in focus towards modular designs that …

Adaptive backpressure: Efficient buffer management for on-chip networks

DU Becker, N Jiang… - 2012 IEEE 30th …, 2012 - ieeexplore.ieee.org
This paper introduces Adaptive Backpressure, a novel scheme that improves the utilization
of dynamically managed router input buffers by continuously adjusting the stiffness of the …

Efficient dynamic virtual channel organization and architecture for NoC systems

M Oveis-Gharan, GN Khan - IEEE Transactions on Very Large …, 2015 - ieeexplore.ieee.org
A growing number of processing cores on a chip require an efficient and scalable
communication structure such as network on chip (NoC). The channel buffer organization of …

Opportunistic caching in noc: exploring ways to reduce miss penalty

A Das, A Kumar, J Jose, M Palesi - IEEE Transactions on …, 2021 - ieeexplore.ieee.org
Due to limited on-chip caching, data-driven applications with large memory footprint
encounter frequent cache misses. Such applications suffer from recurring miss penalty when …

A multi-VC dynamically shared buffer with prefetch for network on chip

H Zhang, K Wang, Y Dai, L Liu - 2012 IEEE Seventh …, 2012 - ieeexplore.ieee.org
In this paper, we propose a novel multi-VC dynamically shared buffer named DAMQ-PF for
network on chip to decrease the memory and area requirement of statically allocating …

Latency improvement by using fill VC allocation for network on chip

M Katta, TK Ramesh - Data Engineering and Communication Technology …, 2021 - Springer
Abstract Network on Chip (NoC) is gaining popularity as an interconnect structure for
complex multicore system on chip. The overall performance of NoC can be enhanced by …

A shared self-compacting buffer for network-on-chip systems

J Liu, JG Delgado-Frias - 2006 49th IEEE international midwest …, 2006 - ieeexplore.ieee.org
In this paper we present a novel shared buffer scheme for systems on chip applications that
require an interconnection network. The proposed scheme is based on a dynamically …

A fast and fair shared buffer for high-radix router

H Zhang, K Wang, J Zhang, N Wu… - Journal of Circuits, Systems …, 2014 - World Scientific
High-radix router based on the tile structure requires large amount of buffer resources. To
reduce the buffer space requirement without degrading the throughput of the router, shared …

Designing Data-Aware Network-on-Chip for Performance

A Das, J Jose - … IEEE Computer Society Annual Symposium on …, 2022 - ieeexplore.ieee.org
Network-on-Chip (NoC) is a widely adopted communication infrastructure in Tiled Chip Multi-
Processors (TCMPs) due to its high transfer bandwidth, scalability and reliability. As the …

Streaming, plaintext private information retrieval using regular expressions on arbitrary length search strings

RA Fink, DR Zaret, RB Stonehirsch… - … IEEE Symposium on …, 2017 - ieeexplore.ieee.org
Submitting a query to a plaintext stream can compromise search privacy, revealing the
interests and motivations of the submitting party to the data owner. Current research in …