OSCAR: Orchestrating STT-RAM cache traffic for heterogeneous CPU-GPU architectures
As we integrate data-parallel GPUs with general-purpose CPUs on a single chip, the
enormous cache traffic generated by GPUs will not only exhaust the limited cache capacity …
enormous cache traffic generated by GPUs will not only exhaust the limited cache capacity …
BiNoCHS: Bimodal network-on-chip for CPU-GPU heterogeneous systems
A Mirhosseini, M Sadrosadati, B Soltani… - Proceedings of the …, 2017 - dl.acm.org
CPU-GPU heterogeneous systems are emerging as architectures of choice for high-
performance energy-efficient computing. Designing on-chip interconnects for such systems …
performance energy-efficient computing. Designing on-chip interconnects for such systems …
Energy-efficient time-division multiplexed hybrid-switched noc for heterogeneous multicore systems
NoCs are an integral part of modern multicore processors, they must continuously support
high-throughput low-latency on-chip data communication under a stringent energy budget …
high-throughput low-latency on-chip data communication under a stringent energy budget …
HyWin: Hybrid wireless NoC with sandboxed sub-networks for CPU/GPU architectures
Heterogeneous System Architectures (HSA) that integrate cores of different architectures
(CPU, GPU, etc.) on single chip are gaining significance for many class of applications to …
(CPU, GPU, etc.) on single chip are gaining significance for many class of applications to …
BARAN: Bimodal adaptive reconfigurable-allocator network-on-chip
A Mirhosseini, M Sadrosadati… - ACM Transactions on …, 2019 - dl.acm.org
Virtual channels are employed to improve the throughput under high traffic loads in
Networks-on-Chips (NoCs). However, they can impose non-negligible overheads on …
Networks-on-Chips (NoCs). However, they can impose non-negligible overheads on …
An efficient dvs scheme for on-chip networks using reconfigurable virtual channel allocators
M Sadrosadati, A Mirhosseini… - 2015 IEEE/ACM …, 2015 - ieeexplore.ieee.org
Network-on-Chip (NoC) is a key element in the total power consumption of a chip
multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs …
multiprocessor. Dynamic Voltage Scaling is a promising method for power saving in NoCs …
Reducing power consumption of GPGPUs through instruction reordering
H Aghilinasab, M Sadrosadati… - Proceedings of the …, 2016 - dl.acm.org
Execution units in GPGPU consume much static power. However, reducing the static power
of execution units is not clear based on two reasons. First, the very long idle time of …
of execution units is not clear based on two reasons. First, the very long idle time of …
Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach
DM Ancajas, K Chakraborty… - 2013 Design, Automation & …, 2013 - ieeexplore.ieee.org
The emergence of power efficient heterogeneous NoCs presents an intriguing challenge in
NoC reliability, particularly due to aging degradation. To effectively tackle this challenge, this …
NoC reliability, particularly due to aging degradation. To effectively tackle this challenge, this …
An efficient DVS scheme for on-chip networks
M Sadrosadati, A Mirhosseini, N Akbarzadeh… - Advances in …, 2022 - Elsevier
Abstract Network-on-Chips (NoCs) consume a significant portion of multiprocessors' total
power. Dynamic Voltage Scaling (DVS) which can reduce both static and dynamic power …
power. Dynamic Voltage Scaling (DVS) which can reduce both static and dynamic power …
A power-performance balanced network-on-chip for mixed CPU-GPU systems
A Mirhosseini, M Sadrosadati, B Soltani… - Advances in …, 2022 - Elsevier
CPU-GPU integrated systems are emerging as a high-performance and easily-
programmable heterogeneous platform to facilitate development of data-parallel software …
programmable heterogeneous platform to facilitate development of data-parallel software …