Cache-coherence protocols have been one of the greatest challenges in formal verification
of hardware, due to their central complication of executing multiple memory-access …

The end of Moore's law and Dennard scaling is shifting the typical computing paradigm
towards Approximate Computing. This paper aims to explain an enhanced version of the …

Designing directory cache coherence protocols is complicated because coherence
transactions are not atomic in modern multicore processors. A coherence transaction …

Energy consumption has become an essential factor in designing modern computer system
architecture. Because of physical limits, the termination of Moore's law and Dennard's …

Implementing cache-coherent shared memory in heterogeneous systems is challenged by
memory consistency model (MCM) mismatches among compute elements: what the system …

In recent years, single-threaded hardware performance has stagnated due to transistor-level
limitations stemming from the end of Moore's Law and Dennard scaling. Instead, today's …

Cache-coherence protocols have been one of the greatest correctness challenges of the
hardware world. A memory subsystem usually consists of several caches and the main …

Cache coherence protocols are often specified using only stable states and atomic
transactions for a single cache hierarchy level. Designing highly-concurrent, hierarchical …

Examples include techniques for near data acceleration for a multi-core architecture. A near
data processor included in a memory controller of a processor may access data main tained …

The emerging Die-stacking technology enables DRAM to be used as a cache to break the
“Memory Wall” problem. Recent studies have proposed to use DRAM as a victim cache in …