A 3-GHz dual-modulus prescaler based on improved master-slave DFF
X Jiahui, W Zhigong, T Lu, X Jian - 2010 IEEE 12th …, 2010 - ieeexplore.ieee.org
An integrated low-power 3-GHz dual-modulus prescaler (DMP) divided-by-32/33 with a
great tolerance to the clock-edge is presented in this paper. A novel structure of CMOS MS …
great tolerance to the clock-edge is presented in this paper. A novel structure of CMOS MS …
A wideband low power low phase noise dual-modulus prescaler
X Lei, Z Wang, K Wang - Journal of Semiconductors, 2011 - iopscience.iop.org
This paper describes a novel divide-by-32/33 dual-modulus prescaler (DMP). Here, a new
combination of DFF has been introduced in the DMP. By means of the cooperation and …
combination of DFF has been introduced in the DMP. By means of the cooperation and …
An improved fully integrated, high-speed, dual-modulus divider
Z Sun, Y Xu, G Ma, H Shi, F Zhao… - Journal of …, 2014 - iopscience.iop.org
A fully integrated 2 n/2 n+ 1 dual-modulus divider in GHz frequency range is presented. The
improved structure can make all separated logic gates embed into correlative D flip—flops …
improved structure can make all separated logic gates embed into correlative D flip—flops …
A 4 GHz quadrature output fractional-N frequency synthesizer for an IR-UWB transceiver
G Shita, H Lu, Y Haiquan, F Lisong… - Journal of …, 2010 - iopscience.iop.org
This paper describes a 4 GHz fractional-N frequency synthesizer for a 3.1 to 5 GHz IR-UWB
transceiver. Designed in a 0.18 μm mixed-signal & RF 1P6M CMOS process, the operating …
transceiver. Designed in a 0.18 μm mixed-signal & RF 1P6M CMOS process, the operating …