A new adaptive selection strategy for reducing latency in networks on chip

M Trik, H Akhavan, AM Bidgoli, AMNG Molk, H Vashani… - Integration, 2023 - Elsevier
Networks on chips (NoCs) are a concept inspired by computer networks for constructing
multiprocessor systems that can handle communication across processing cores. One of the …

A hybrid selection strategy based on traffic analysis for improving performance in networks on chip

M Trik, AMNG Molk, F Ghasemi… - Journal of …, 2022 - Wiley Online Library
Networks on chip (NoCs) are an idea for implementing multiprocessor systems that have
been able to handle the communication between processing cores, inspired by computer …

[PDF][PDF] Design and simulation of ring network-on-chip for different configured nodes

A Jain, RK Dwivedi, H Alshazly, A Kumar… - … Materials & Continua, 2022 - cdn.techscience.cn
The network-on-chip (NoC) technology is frequently referred to as a front-end solution to a
back-end problem. The physical substructure that transfers data on the chip and ensures the …

HDL Environment for the Synthesis of 2-Dimensional and 3-Dimensional Network on Chip Mesh Router Architecture

S Kumari, K Rajput, G Singh, A Jain… - 2024 International …, 2024 - ieeexplore.ieee.org
Application specific Network on Chip (NoC) designs are quickly becoming the technology of
choice for solving the problem of multiprocessor system architecture. Broadband, interposes …

[PDF][PDF] Smart Communication Using 2D and 3D Mesh Network-on-Chip.

A Jain, A Kumar, AP Shukla, H Alshazly… - … Automation & Soft …, 2022 - researchgate.net
Network on chip (NoC) is an integrated communication system on chip (SoC), efficiently
connecting various intellectual property (IP) modules on a single die. NoC has been …

Scalable networks-on-chip interconnected architecture for astrocyte-neuron networks

J Liu, J Harkin, LP Maguire, LJ McDaid… - … on Circuits and …, 2016 - ieeexplore.ieee.org
Spiking astrocyte-neuron networks (ANNs) have the potential to emulate the self-repair
capability in the mammalian brain. Recent research has explored the mimicking of this …

Fault-tolerant networks-on-chip routing with coarse and fine-grained look-ahead

J Liu, J Harkin, Y Li, LP Maguire - IEEE transactions on …, 2015 - ieeexplore.ieee.org
Fault tolerance and adaptive capabilities are challenges for modern networks-on-chip (NoC)
due to the increase in physical defects in advanced manufacturing processes. Two novel …

Adding security to networks-on-chip using neural networks

K Madden, J Harkin, L McDaid… - 2018 IEEE Symposium …, 2018 - ieeexplore.ieee.org
Modern computing systems are using Networkson-Chip (NoCs) for scalable on-chip
communications. Traditional security attacks have focused on the computing cores however …

A network adaptive fault-tolerant routing algorithm for demanding latency and throughput applications of network-on-a-chip designs

Z Nain, R Ali, S Anjum, MK Afzal, SW Kim - Electronics, 2020 - mdpi.com
Scalability is a significant issue in system-on-a-chip architectures because of the rapid
increase in numerous on-chip resources. Moreover, hybrid processing elements demand …

Self-repairing mobile robotic car using astrocyte-neuron networks

J Liu, J Harkin, L McDaid, DM Halliday… - … Joint Conference on …, 2016 - ieeexplore.ieee.org
A self-repairing robot utilising a spiking astrocyte-neuron network is presented in this paper.
It uses the output spike frequency of neurons to control the motor speed and robot activation …