This article introduces a probabilistic machine learning framework for the uncertainty
quantification (UQ) of electronic circuits based on the Gaussian process regression (GPR) …

The failure rate of static RAM (SRAM) cells is restricted to be extremely low to ensure
sufficient high yield for the entire chip. In addition, multiple performances of interest and …

As the technology node shrinks to the nanometer scale, process variation become one of the
most important issues in IC designs. The industry calls for designs with high yield under …

Leveraging machine learning has been proven as a promising avenue for addressing many
practical circuit design and verification challenges. We demonstrate a novel active learning …

The impact of process variation to advanced integrated circuits has become increasingly
significant. Traditional sampling based yield analysis and optimization always require large …

As high-density SRAMs must be designed to ensure a substantially small failure rate, the
accurate yield estimation with practically acceptable runtime of circuit simulations is highly …

In this brief, a pMOS pass gate (PPG) local bitline static random access memory (LB SRAM)
architecture is proposed to reduce the read delay and resolve the half-select issue with a …

Computationally intensive simulations have made analog circuit sizing challenging for
complicated analog circuit performance characterization. Accurate yet computationally …

With increasing dimension of variation space and computational intensive circuit simulation,
accurate and fast yield estimation of realistic SRAM chip remains a significant and …

Developments over the last decades in very large-scale integration technologies allowed
meeting the increasing demand for faster, cheaper, and reliable electronic devices. One of …