Design of Low-Power High-Efficient Single-Tail Comparator Using 180 nm CMOS Technology
R Nagore, PK Jain, RS Gamad… - … , Machine Learning and …, 2022 - Springer
Promoting dynamic single-tail comparators to optimize input speed and productivity is the
clandestine to low-cost, area-efficient, high-speed analog to digital converters. An overview …
clandestine to low-cost, area-efficient, high-speed analog to digital converters. An overview …
Analysis and design of low power consumption 8t and 10t full adder cmos technology
MIB Abd Majid, R Sahak… - 2022 IEEE 13th …, 2022 - ieeexplore.ieee.org
All designers and engineers are familiar with the significance of adder subsystems.
Therefore, engineers continue to perform research on them by integrating creative design …
Therefore, engineers continue to perform research on them by integrating creative design …
CMOS binary image sensor with gate/body-tied PMOSFET-type photodetector for low-power and low-noise operation
J Lee, BS Choi, D Seong, J Lee, SH Kim… - Journal of Sensor …, 2018 - koreascience.kr
A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for
low-power and low-noise operation. The proposed binary image sensor has the advantages …
low-power and low-noise operation. The proposed binary image sensor has the advantages …
Comparative Analysis of Preamplifiers for Comparators.
In low power electronics technology, a lot of new technology has already been introduced to
reduce the power consumption of comparator. This paper presents the comparative study of …
reduce the power consumption of comparator. This paper presents the comparative study of …
Design of a low power dynamic comparator in 180nm CMOS technology
A Mishra, M Kumar - 2018 International Conference on …, 2018 - ieeexplore.ieee.org
This paper aimed towards compact and low power dynamic CMOS comparator in 180nm
technology with supply voltage of 1.8 V. Comparator is proposed in this paper using circuit …
technology with supply voltage of 1.8 V. Comparator is proposed in this paper using circuit …
A modified dynamic comparator for lowering peak kink in differential amplifier and latch
V Dhandapani, A Mishra, R Mishra… - AIP Conference …, 2023 - pubs.aip.org
A dynamic comparator usually has two stages; differential amplifier as stage 1 and latch-
based circuitry as stage 2. A differential amplifier amplifies the difference in the input …
based circuitry as stage 2. A differential amplifier amplifies the difference in the input …