Pulsed-latch circuits retain the advantages of both latches and flip-flops, offering higher
performance and lower power consumption within a conventional ASIC design environment …

In this work, the performance of ring counter is improved using pulsed latch technique. In
high speed and low power VLSI applications where heavy pipelining is used, there is …

Pulsed-latches emerge as an ideal sequencing element for low power digital circuit design,
serving as an alternative of flip-flops. In this paper, low power multi-bit pulsed-latches are …

Minimizing the size of a clock tree is known as an effective approach to reduce power
dissipation in modern circuit designs. However, most existing power-aware clock-tree …

In this study, a novel power efficient implicit pulsed‐triggered flip‐flop with embedded clock‐
gating and pull‐up control scheme (IPFF‐CGPC) is proposed. By applying an XOR‐based …

A pulsed-latch can be modeled as a fast flip-flop. This allows conventional flip-flop designs
to be migrated to pulsed-latch versions by simple replacement to reduce the clocking power …

A novel dual-edge implicit pulse-triggered flip-flop with an embedded clock-gating scheme
(DIFF-CGS) is proposed, which employs a transmission-gate-logic (TGL) based clock-gating …

Minimizing the clock tree has been known as an effective approach to reduce power
dissipation in modern circuit designs. However, most existing power-aware clock tree …

Gate-level clock gating starts with a netlist, with partial or no gating applied; some flip-flops
are then selected for further gating to reduce the circuit's power consumption, and a gating …

Flip-flops are the most common form of sequencing elements; however, they have a
significantly higher sequencing overhead than latches in terms of delay, power, and area …