Recent advances in semiconductor technology offer vertical interconnect access (via) that
extend through silicon, popularly known as through silicon via (TSV). This book provides a …

This paper is concerned with the analysis and optimization of the ground bounce in digital
CMOS circuits. First, an analytical method for calculating the ground bounce is presented …

As the feature size of integrated circuits shrinking in deep submicron technologies, time
delay, and crosstalk noise of complementary metal-oxide-semiconductor (CMOS)-gate …

This textbook comprehensively covers on-chip interconnect dimension and application of
carbon nanomaterials for modeling VLSI interconnect and buffer circuits. It provides analysis …

This paper deals with the problem of estimating the performance of a CMOS gate driving
RLC interconnect load. The widely accepted model for CMOS gate and interconnect line is …

Nowadays, the interconnect circuits' conduct plays a crucial role in determining the
performance of the CMOS systems, especially those related to nano-scale technology …

Artificial neural networks are applied for modeling the input and output circuits of the digital
part of the digital–analog and analog–digital interface, respectively, in CMOS mixed-mode …

An effective capacitance of a distributed RLC load for estimating short-circuit power is
presented in this paper. Both resistive and inductive shielding effects of interconnects are …

As VLSI technologies scale down, the average die size is expected to remain constant or to
slightly increase with each generation. This results in an average increase in the global …

This paper introduces a numerical method for time domain analysis of the inverter driving
interconnect in CMOS digital integrated circuits. To include the carriers' velocity saturation …