Fully depleted SOI (FDSOI) technology
K Cheng, A Khakifirooz - Science China Information Sciences, 2016 - Springer
Fully depleted SOI (FDSOI) has become a viable technology not only for continued CMOS
scaling to 22 nm node and beyond but also for improving the performances of legacy …
scaling to 22 nm node and beyond but also for improving the performances of legacy …
GAAFET versus pragmatic FinFET at the 5nm Si-based CMOS technology node
YC Huang, MH Chiang, SJ Wang… - IEEE Journal of the …, 2017 - ieeexplore.ieee.org
Speed and power performances of Si-based stacked-nanowire gate-all-around (GAA) FETs
and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected …
and pragmatic ultra-thin-fin FETs at the 5nm CMOS technology node are projected …
CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology
HH Radamson, Y Miao, Z Zhou, Z Wu, Z Kong, J Gao… - Nanomaterials, 2024 - mdpi.com
After more than five decades, Moore's Law for transistors is approaching the end of the
international technology roadmap of semiconductors (ITRS). The fate of complementary …
international technology roadmap of semiconductors (ITRS). The fate of complementary …
Planar fully-depleted-silicon-on-insulator technologies: Toward the 28 nm node and beyond
This paper presents a comprehensive overview of the research done in the last decade on
planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint …
planar Fully-Depleted-Silicon-On-Insulator (FDSOI) technologies in the frame of the joint …
Vertical slit FET at 7-nm node and beyond
PL Yang, TB Hook, PJ Oldiges… - IEEE Transactions on …, 2016 - ieeexplore.ieee.org
This paper investigates the n-type vertical slit FET (VeSFET) performance at 7-nm node and
beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration …
beyond by TCAD simulation. VeSFET is a twin-gate device with 3-D monolithic integration …
Ti-states: Processor power management in the temperature inversion region
Temperature inversion is a transistor-level effect that can improve performance when
temperature increases. It has largely been ignored in the past because it does not occur in …
temperature increases. It has largely been ignored in the past because it does not occur in …
Mobility of circular and elliptical Si nanowire transistors using a multi-subband 1D formalism
C Medina-Bailon, T Sadi, M Nedjalkov… - IEEE Electron …, 2019 - ieeexplore.ieee.org
We have studied the impact of the cross-sectional shape on the electron mobility of n-type
silicon nanowire transistors (NWTs). We have considered circular and elliptical cross-section …
silicon nanowire transistors (NWTs). We have considered circular and elliptical cross-section …
InAs FinFETs With nm Fabricated Using a Top–Down Etch Process
R Oxland, X Li, SW Chang, SW Wang… - IEEE Electron …, 2016 - ieeexplore.ieee.org
We report the first demonstration of InAs FinFETs with fin width in the range 25–35 nm,
formed by inductively coupled plasma etching. The channel comprises defect-free, lattice …
formed by inductively coupled plasma etching. The channel comprises defect-free, lattice …
Simulation study of the impact of quantum confinement on the electrostatically driven performance of n-type nanowire transistors
Y Wang, T Al-Ameri, X Wang… - … on Electron Devices, 2015 - ieeexplore.ieee.org
In this paper, we have studied the impact of quantum confinement on the performance of n-
type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies …
type silicon nanowire transistors (NWTs) for application in advanced CMOS technologies …
UTBB FDSOI: Evolution and opportunities
S Monfray, T Skotnicki - Solid-State Electronics, 2016 - Elsevier
As today's 28 nm FDSOI (Fully Depleted Silicon On Insulator) technology is at the
industrialization level, this paper aims to summarize the key advantages allowed by the thin …
industrialization level, this paper aims to summarize the key advantages allowed by the thin …