Design optimization techniques in nanosheet transistor for RF applications
Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated
TCAD simulations. The effects of stack spacing and number of stacks on device performance …
TCAD simulations. The effects of stack spacing and number of stacks on device performance …
Fast-switching tri-anode Schottky barrier diodes for monolithically integrated GaN-on-Si power circuits
Tri-Anode GaN Schottky Barrier Diodes (SBDs) have recently shown excellent DC
performance with low turn-on voltage and large breakdown thanks to their 3D contact …
performance with low turn-on voltage and large breakdown thanks to their 3D contact …
Beyond the highs and lows: A perspective on the future of dielectrics research for nanoelectronic devices
High-dielectric constant (high-k) gate oxides and low-dielectric constant (low-k) interlayer
dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past …
dielectrics (ILD) have dominated the nanoelectronic materials research scene over the past …
A predictive 3-D source/drain resistance compact model and the impact on 7 nm and scaled FinFETs
Due to the increasing importance and complexity of source/drain parasitic resistance (Rsd)
in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware Rsd …
in nanoscale CMOS technology and circuit design, a predictive 3-D structure-aware Rsd …
Hybrid low‐k spacer scheme for advanced FinFET technology parasitic capacitance reduction
Low‐dielectric constant (low‐k) material is critical for advanced FinFET technology parasitic
capacitance reduction to enable low‐power and high‐performance applications. Silicon …
capacitance reduction to enable low‐power and high‐performance applications. Silicon …
Emulation and simulation of microelectronic fabrication processes
X Klemenschits - 2022 - repositum.tuwien.at
The fabrication of increasingly powerful microelectronic processors, enabled by transistor
scaling, has been a main driver of technological progress in most fields since the 1950 s …
scaling, has been a main driver of technological progress in most fields since the 1950 s …
Investigating single event transients of advanced fin based devices for inclusion in ICs
C Dimri, GP Nikhil, PK Mohanty, KP Pradhan… - … -International Journal of …, 2021 - Elsevier
In the present work, various 10 nm FD-SOI FinFET structures utilizing promising design
elements like raised source and drain extensions, hybrid air spacer, and interfacial silicide …
elements like raised source and drain extensions, hybrid air spacer, and interfacial silicide …
Predictive and prospective calibrated TCAD to improve device performances in sub-20 nm gate length p-FinFETs
In this paper we present an extended analysis of thsse impact of SiGe p-epi source/drain
engineering on sub-20 nm gate length p-FinFETs performance for the N7 technology node …
engineering on sub-20 nm gate length p-FinFETs performance for the N7 technology node …
A Comparative Analyze of FinFET and Bulk MOSFET SRAM Design
W Wang - 2022 International Conference on Applied Physics …, 2022 - ieeexplore.ieee.org
FinFET technology has become the most popular topic in submicron SoC and VSLI design
in recent years, attributable to its numerous advantages, including excellent scalability and …
in recent years, attributable to its numerous advantages, including excellent scalability and …
Combined Process Simulation and Emulation of an SRAM Cell of the 5nm Technology Node
X Klemenschits, S Selberherr… - … on Simulation of …, 2021 - ieeexplore.ieee.org
Fast geometric process emulation models were combined with sophisticated physical
simulations on a common simulation platform. In order to show the capabilities of this …
simulations on a common simulation platform. In order to show the capabilities of this …