Monolithic 180 nm CMOS dosimeter for in vivo medical applications

EG Villani, A Gabrielli, A Khan, E Pikhay… - … on Nuclear Science, 2013 - ieeexplore.ieee.org
The design and development of a monolithic system-on-chip silicon device for real time
measurement of radiation dose is described. The device is fabricated in a standard 180 nm …

A low-cost low-power non-volatile memory for RFID applications

H Dagan, A Teman, A Fish, E Pikhay… - … on Circuits and …, 2012 - ieeexplore.ieee.org
One of the main obstacles delaying a more widespread use of radio frequency identification
(RFID) tags is cost. A critical element of any RFID system is a low power embedded non …

A low-power DCVSL-like GIDL-free voltage driver for low-cost RFID nonvolatile memory

H Dagan, A Teman, E Pikhay, V Dayan… - IEEE journal of solid …, 2013 - ieeexplore.ieee.org
<? Pub Dtl=""?> The realization of a low-cost passive radio frequency identification (RFID)
tag requires the ability to fabricate the system in a bulk CMOS process without any additional …

Non-volatile memories in the foundry business

A Strum, T Mahlen, Y Roizin - 2010 IEEE International Memory …, 2010 - ieeexplore.ieee.org
The role of non-volatile memory (NVM) technologies in the business of silicon foundries is
reviewed. Solutions that comply with the NVM requests of diverse customers in today's …

Very dense NVM bitcell

AE Horch - US Patent 8,598,642, 2013 - Google Patents
Embodiments relate to a nonvolatile memory (“NVM) bitcell with reduced size and enhanced
capacitive coupling between the source and the floating gate. The bitcell may use band to …

Array operation mode characterization of select gate lateral coupling single-poly embedded nonvolatile memory

SK Park, NY Kim, KI Choi - IEEE Transactions on Electron …, 2016 - ieeexplore.ieee.org
This paper clarifies the reason for the specific array structure and operation methods of a
select gate lateral coupling (SGLC) cell array as well as its disturbance immunity. An SGLC …

[图书][B] Design Rules in a Semiconductor Foundry

E Shauly - 2022 - api.taylorfrancis.com
Nowadays over 50% of the integrated circuits are manufactured at wafer foundries. This
book presents a foundry-integrated perspective of the field and is a comprehensive and up …

Dedicated Design Rules for Memory Modules

Y Roizin, E Pikhay, EN Shauly - Design Rules in a Semiconductor …, 2022 - taylorfrancis.com
The nominal voltages are often higher than for the core CMOS, and the physical design of
the devices is different. The periphery devices' DRs are typically looser than for CMOS …

A GIDL free tunneling gate driver for a low power non-volatile memory array

H Dagan, A Teman, A Fish, E Pikhay… - … on Circuits and …, 2012 - ieeexplore.ieee.org
A recently presented single-poly non-volatile C-Flash memory bitcell provides an ultra-low
power low cost option for embedded RFID design. This cell requires the application of a 10V …

Very dense nonvolatile memory bitcell

AE Horch - US Patent 9,355,728, 2016 - Google Patents
An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and
drain regions comprising carriers of the same conductivity type. A floating gate rests on top …