Advances of metaheuristic algorithms in training neural networks for industrial applications

HY Chong, HJ Yap, SC Tan, KS Yap, SY Wong - Soft Computing, 2021 - Springer
In recent decades, researches on optimizing the parameter of the artificial neural network
(ANN) model has attracted significant attention from researchers. Hybridization of superior …

3D‐IC partitioning method based on genetic algorithm

NY Meitei, KL Baishnab… - IET Circuits, Devices & …, 2020 - Wiley Online Library
In this study, a new tier partitioning algorithm for three‐dimensional integrated circuits (3D
ICs) using a genetic algorithm (GA) is presented. Design parameters for the proposed 3D IC …

Integrated Taguchi-simulated annealing (SA) approach for analyzing wear behaviour of silicon nitride

S Ghalme, A Mankar, Y Bhalerao - Journal of applied research and …, 2017 - scielo.org.mx
In this study, the integrated Taguchi-simulated annealing (SA) approach is applied to
examine the wear behaviour of silicon nitride (Si 3 N 4)-hexagonal boron nitride (hBN) …

An efficient partitioning and placement based fault TSV detection in 3D-IC using deep learning approach

RK Radhakrishnan Nair, S Pothiraj… - Journal of Ambient …, 2021 - Springer
Over topical eras, three dimensional Integrated Circuit (3D-IC) fabrications have become
vital among the researchers and industrial people, owing to its wide range of amenities …

TSV aware 3D IC partitioning with area optimization

JP Kadambarajan, S Pothiraj - Arabian Journal for Science and …, 2021 - Springer
A paradigm shift has been witnessed in microelectronic industry in recent days with more
and more research works focusing on transformation of Integrated Circuits from 2 to 3D …

An efficient 3D IC partitioning approach using satin bowerbird optimization for reduced TSV count and improved heat dissipation

S Roy, S Banerjee - Engineering Research Express, 2023 - iopscience.iop.org
Net list partitioning achieves paramount importance in the physical architecture design step
of Three Dimensional (3D) Very Large Scale Integrated (VLSI) circuits. The performance of …

Simultaneous optimization of the area, wirelength and TSVs in a 3D IC design

A Prakash, RK Lal - Sādhanā, 2022 - Springer
The technology of a three-dimensional integrated circuit (3D-IC) is an emerging approach
for improving performance. In comparison to a standard 2-D IC design, which arranges all of …

3D IC partitioning approach for achieving lower TSV count and reduced heat dissipation using particle swarm optimization

S Roy, S Banerjee - 2022 First International Conference on …, 2022 - ieeexplore.ieee.org
Partitioning is the preliminary stage in the VLSI physical design process, and it impacts the
outcome of all following physical design steps such as floor planning, placement, pin …

Genetic Algorithm Based 3D IC Partitioning Approach for TSV Minimization and Efficient Layer Assignment

S Roy, S Banerjee - IETE Journal of Research, 2024 - Taylor & Francis
The rise of three-dimensional (3D) IC layouts necessitates the development of unique
partitioning methods that will be suitable for the 3D component designs. Net lists partitioning …

Optimization of Placement and Routing Techniques: Congestion Estimation and Control in VLSI Design

V Nagendra, S Manavalan - … on Data Science, Machine Learning and …, 2023 - Springer
The rapid advancement of integrated circuit (IC) technology has increased the demand for
efficient and effective VLSI optimization methods. This paper presents a systematic literature …