C Gao, X Meng, W Li, J Lai, Y Zhang… - 2024 USENIX Annual …, 2024 - usenix.org
The increasing prevalence of new Instruction Set Architectures (ISAs) necessitates the migration of closed-source binary programs across ISAs. Dynamic Binary Translation (DBT) …
H Ponce-de-León, F Furbach… - 2018 Formal Methods …, 2018 - ieeexplore.ieee.org
This paper reports progress in verification tool engineering for weak memory models. We present two bounded model checking tools for concurrent programs. Their distinguishing …
N Liu, B Zang, H Chen - Proceedings of the 25th ACM SIGPLAN …, 2020 - dl.acm.org
In this paper, we present the first comprehensive performance characterization and optimization of ARM barriers on both mobile and server platforms. We draw a set of …
When mapping C programs to hardware, high-level synthesis (HLS) tools seek to reorder instructions so they can be packed into as few clock cycles as possible. However, when …
M Taheri, A Pourdamghani… - … Symposium on Distributed …, 2019 - drops.dagstuhl.de
To enhance performance, common processors feature relaxed memory models that reorder instructions. However, the correctness of concurrent programs is often dependent on the …
Many hardware and compiler optimisations introduced to speed up single-threaded programs also introduce additional, sometimes surprising, behaviours for concurrent …
When mapping C programs to hardware, highlevel synthesis (HLS) tools reorder independent instructions, aiming to obtain a schedule that requires as few clock cycles as …
S Chakraborty - arXiv preprint arXiv:2009.03846, 2020 - arxiv.org
Mapping programs from one architecture to another plays a key role in technologies such as binary translation, decompilation, emulation, virtualization, and application migration …
To improve efficiency of memory accesses, modern multiprocessor architectures implement a whole range of different weak memory models. The behavior of performance-critical code …