This paper presents a 28-Gb/s transceiver in 32-nm SOI CMOS technology for chip-to-chip
communications over high-loss electrical channels such as backplanes. The equalization …

While four-level pulse amplitude modulation (PAM4) standards are emerging to increase
bandwidth density, the majority of standards use simple binary non-returnto-zero (NRZ) …

A 40 Gb/s serial link interface is presented that includes four lanes of transceiver optimized
for chip-to-chip communication while compensating for 20 dB of channel loss. Transmit …

A compact and power-efficient serial I/O targeting dense silicon carrier interconnects is
reported. Based on expected channel characteristics, the proposed I/O features low …

This paper presents the design of a 19-Gb/s serial link receiver with both 4-tap feed-forward
equalizer (FFE) and 5-tap decision-feedback equalizer (DFE), thereby making the …

This paper introduces a fully-integrated wireline transceiver operating at 40 Gb/s. The
transmitter incorporates a 5-tap finite-inpulse response (FIR) filter with LC-based delay lines …

This study provides a comprehensive review of decision feedback equalisation (DFE) for
multi‐giga‐bit‐per‐second (Gbps) data links. The state‐of‐the‐art of DFE for multi‐Gbps …

A source synchronous I/O system based on high-density silicon carrier interconnects is
introduced. Benefiting from the advantages of advanced silicon packaging technologies, the …

A low-power receiver circuit in 32 nm SOI CMOS is presented, which is intended to be used
in a source-synchronous link configuration. The design of the receiver was optimized for …

This brief presents an adaptive continuous-time linear equalizer (CTLE) and one-tap
decision feedback equalizer (DFE) using the spectrum balancing (SB) method. The SB …