RTL Design and Logic Synthesis of Traffic Light Controller for 45nm Technology

A Devipriya, H Girish, V Srinivas… - 2022 3rd …, 2022 - ieeexplore.ieee.org
In many cities, traffic regulation is a difficult challenge to solve. This is due to the large
number of cars and the traffic system's high dynamics. Poor traffic network are a major cause …

[PDF][PDF] A comparative analysis of finfet based sram design

V Kumbar, M Waje - IJEER, 2022 - pccoer.com
░ ABSTRACT-FinFETs are widely used as efficient alternatives to the single gate general
transistor in technology scaling because of their narrow channel characteristic. The width …

A Low-Power and High-Stability 8T SRAM Cell with Diode-Connected Transistors

M Elangovan, M Muthukrishnan - Journal of Circuits, Systems and …, 2022 - World Scientific
This research paper proposes a low-power, high-stability 8T static random access memory
(SRAM) cell. The proposed SRAM cell is a modified structure of the conventional 6T SRAM …

Design and technology co-optimization for investigating power, performance, area and cost trade-offs in FinFET technologies

V Kumbar, V Raut - ICCCE 2021: Proceedings of the 4th International …, 2022 - Springer
The speed of the semiconductor technology roadmap was conventionally defined by the
scaling of the patterning pitches, with the main objective of halving the cost per transistor for …

SECURE SMART DOOR LOCK FEATURING FACIAL RECOGNITION

KR Mamatha, S Thejaswini… - Machine …, 2024 - machineintelligenceresearchs.com
Identity fraud has become a big concern in today's society which increasing number of risks.
A face recognition system must be built to prevent these thefts and identity fraud. For the …

Performance Analysis of FinFET-Based Static Random Access Memory Design

V Kumbar, M Waje - 2022 International Conference on Smart …, 2022 - ieeexplore.ieee.org
The short-channel effect (SCE) limits the performance of planar MOSFET devices in
conventional complementary metal oxide semiconductor (CMOS) technologies due to the …

Design And Validation Of A 32-Bit RISC-V Processor Incorporating Vedic Mathematics

H Girish, V Shylaja, D Vijayalakshmi… - … : Theory and Practice, 2024 - kuey.net
A Vedic multiplier architecture is employed in constructing a 32-bit RISC-V processor to
enhance speed and reduce computational complexity. It's ALU and MAC units, based on …

[PDF][PDF] Performance Evaluation Of AI Models In Early Heart Disease Diagnosis

S Thejaswini - … Administration: Theory and Practice, 30 (2), 2024 - researchgate.net
Machine learning is increasingly being utilized throughout various stages of healthcare,
particularly in predicting conditions like locomotor disorders and heart disease. Treating …

[PDF][PDF] Laser Fencing Surveillance System With Email Alert

KR Mamatha - … Administration: Theory and Practice, 30 (2), 2024 - researchgate.net
This work presents an antitheft alert system that integrates multiple technologies to offer a
high level of detection, monitoring, and barrier protection through costeffective methods and …

[PDF][PDF] Collision Alert System for Vehicles Using GSM Technology

SK Suhas, H Girish, MK Revathi, MK Gayathiri - researchgate.net
Road accidents represent a grave global concern, causing tragic fatalities worldwide. India
currently tops the list of nations grappling with this issue, necessitating immediate attention …