Machine learning for FPGA electronic design automation

A Biscontini, E Popovici, A Temko - IEEE Access, 2024 - ieeexplore.ieee.org
In the last decades, field-programmable gate arrays (FPGAs) have become increasingly
important to the electronics industry, offering higher performance and lower power …

Survey of machine learning for software-assisted hardware design verification: Past, present, and prospect

N Wu, Y Li, H Yang, H Chen, S Dai, C Hao… - ACM Transactions on …, 2024 - dl.acm.org
With the ever-increasing hardware design complexity comes the realization that efforts
required for hardware verification increase at an even faster rate. Driven by the push from …

Accelerating Continuous Integration with Parallel Batch Testing

E Fallahzadeh, AH Bavand, PC Rigby - … of the 31st ACM Joint European …, 2023 - dl.acm.org
Continuous integration at scale is costly but essential to software development. Various test
optimization techniques including test selection and prioritization aim to reduce the cost …

Contrasting test selection, prioritization, and batch testing at scale: Large-scale Empirical Study on 285 Million Test Results

E Fallahzadeh, PC Rigby, B Adams - Empirical Software Engineering, 2025 - Springer
The effectiveness of software testing is crucial for successful software releases, and various
test optimization techniques aim to enhance this process by reducing the number of test …

Optimizing ml classification models for constrained EDA resource budgets

G Parthasarathy, B Kumar, S Nanda… - 2022 IEEE 40th …, 2022 - ieeexplore.ieee.org
Methods based on machine learning (ML) are gaining increasing importance at various
stages of the integrated circuit (IC) design flow including EDA applications. However, real …

Optimizing Constrained Random Verification with ML and Bayesian Estimation

B Kumar, G Parthasarathy, S Nanda… - 2023 ACM/IEEE 5th …, 2023 - ieeexplore.ieee.org
Constrained Random Verification (CRV) is a widely used design verification methodology
that focuses on generating pseudo-random legal transactions or stimuli for the device under …

Acceleration of hardware code coverage closure using machine learning

M Aggoune - 2022 - oulurepo.oulu.fi
With the ever-increasing system-on-chip (SoC) design complexity, the verification of such
systems is becoming more and more challenging and extremely time consuming. Hence, the …

An AI-Assisted Connection Weight Prediction for Regression Testing of Integrated Circuits

A Ravikumar, X Yang, R Prasad… - … on Defect and Fault …, 2024 - ieeexplore.ieee.org
Integrated Circuit (IC) verification, ie the process of ensuring that it performs according to the
design specifications, is highly resource intensive. This often depends on an IC's complexity …

Assessing the Efficacy of Test Selection, Prioritization, and Batching Strategies in the Presence of Flaky Tests and Parallel Execution at Scale

E Fallahzadeh - 2023 - spectrum.library.concordia.ca
Effective software testing is essential for successful software releases, and numerous test
optimization techniques have been proposed to enhance this process. However, existing …

Machine Learning-Driven Paradigms in VLSI Design: Exploring the Synergy with Pruning for Optimal Circuit Efficiency

PD Parameswari… - 2024 Parul International …, 2024 - ieeexplore.ieee.org
This survey paper explores the intersection of machine learning and VLSI design, shedding
light on the evolving landscape of innovative methodologies. The initial focus is on papers …