(57) ABSTRACT A semiconductor package including a top-surface metal layer for
implementing circuit features provides improvements in top-surface interconnect density …

5,672,548 A 9/1997 Culnane et 211. 5,682,061 A 10/1997 Khandros et al. 5,685,885 A
11/1997 Khandros et al. 5,686,699 A 11/1997 Chu et al. 5,734,555 A 3/1998 McMahon …

A semiconductor package including top-surface terminals for mounting another
semiconductor package provides a three-dimensional circuit configuration that can provide …

A semiconductor package including top-surface terminals for mounting another
semiconductor package provides a three-dimensional circuit configuration that can provide …

Surface and a second Surface remote from the first Surface. A microelectronic element
overlies the first Surface and first electrically conductive elements are exposed at one of the …

A high density test probe is for testing a high density and high performance integrated
circuits in wafer form or as discrete chips. The test probe is formed from a dense array of …

(57) ABSTRACT A method for making an interposer includes forming a plurality of wire
bonds bonded to one or more first surfaces of a first element. A dielectric encapsulation is …

A structure may include bond elements having bases joined to (51) Int. Cl. conductive
elements at a first portion of a first Surface and end HOIL 23/02(2006.01) surfaces remote …

BACKGROUND OF THE INVENTION In the microelectronics industry, before integrated
circuit (IC) chips are packaged in an electronic component, such as a computer, they are …

[57] ABSTRACT A plurality of integrated circuit chips (12) are packaged in a stack of chips in
which a number of individual chip layers (10,120,130,132,134) are physically and …