Design insights into RF/analog and linearity/distortion of spacer engineered multi‐fin SOI FET for terahertz applications
VB Sreenivasulu, V Narendar - International Journal of RF and …, 2021 - Wiley Online Library
Multi‐fin devices are the most reliable option for terahertz (THz) frequency applications at
nano‐regime. In this work impact of spacer engineering on multi‐fin SOI FET performance is …
nano‐regime. In this work impact of spacer engineering on multi‐fin SOI FET performance is …
Junctionless gate-all-around nanowire FET with asymmetric spacer for continued scaling
VB Sreenivasulu, V Narendar - Silicon, 2021 - Springer
In this paper, we have performed the scaling of asymmetric junctionless (JL) SOI nanowire
(NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC …
(NW) FET at 10 nm gate length (LG). To study the device electrical performance various DC …
Fatigue behaviour analysis of thermal cyclic loading for through-silicon via structures based on backstress stored energy density
H Qian, Z Huang, H Fan, Y Wang, L Cao, Q Zhu… - International Journal of …, 2024 - Elsevier
Through-silicon via (TSV) structures are widely used in microelectronic due to the ease of
chip interconnection. Few research has focused on investigating the fatigue properties of …
chip interconnection. Few research has focused on investigating the fatigue properties of …
Implementation of smart energy meter through prepaid transaction using IoT
PR Reddy, R Kammanaboina, D Prasad… - … on Recent Trends …, 2021 - ieeexplore.ieee.org
In India, energy meters are electro-mechanical and postpaid. The main drawback of this
approach is that a person must walk from street to street, reading each house's energy meter …
approach is that a person must walk from street to street, reading each house's energy meter …
Microstructure and mechanical properties of copper/al interlayer/graphite joint prepared utilizing “two-stage method” vacuum diffusion bonding
S Zhang, T Ma, Y Zhao, Z Zhang, W Shao, J Huang… - Vacuum, 2024 - Elsevier
Abstract The high property Copper/Graphite joint with Al foil as intermediate layer has been
prepared utilizing the “two-stage method” diffusion bonding. At stage I, the Cu–Al diffusion …
prepared utilizing the “two-stage method” diffusion bonding. At stage I, the Cu–Al diffusion …
Multi-crack spatial propagation evolution analysis of 3D-TSV under thermal-electric-mechanical coupling field
K Hou, Z Fan, Y Chen, S Zhang, Y Wang… - Materials Science in …, 2025 - Elsevier
A bstract As an interconnected microstructure, Through-Silicon Via (TSV) play a vital role in
three-dimension (3D) chip. With the improvement of interconnection density, the reliability …
three-dimension (3D) chip. With the improvement of interconnection density, the reliability …
[PDF][PDF] Junctionless Gate-All-Around Nanowire FET with Asymmetric Spacer for Continued Scaling
BS Vakkalakula, V Narendar - 2021 - scholar.archive.org
In this paper we have performed scaling performance of asymmetric junctionless (JL) SOI
nanowire FET at 10 nm gate length (LG). To study the device electrical performance various …
nanowire FET at 10 nm gate length (LG). To study the device electrical performance various …
Asymmetric Spacer Junctionless GAA Nanowire FET for Continued Scaling
BS Vakkalakula, N Vadthiya - 2021 - researchsquare.com
We demonstrate junctionless (JL) n-channel SOI nanowire FET with asymmetric spacer at
nano regime. The impact of various spacer dielectrics on device performance is presented …
nano regime. The impact of various spacer dielectrics on device performance is presented …