Dense Gaussian networks (DGNs) are suitable topology candidates for network-on-chip
(NoC) architectures because they provide favorable network properties such as symmetry …

Large-scale neural network (NN) accelerators typically consist of several processing nodes,
which could be implemented as a multi-or many-core chip and organized via a network-on …

This work is devoted to the study of application of new topologies in the design of networks-
on-chip (NoCs). It is proposed to use two-dimensional optimal circulant topologies for NoC …

Broadcast efficiency in mobile wireless sensor networks (MWSNs) is greatly influenced by
several factors, such as node energy and mobile elements. Several energy-efficient …

Network cost and fixed-degree characteristic for the graph are important factors to evaluate
interconnection networks. In this paper, we propose hierarchical Petersen network (HPN) …

Applying semiconductor technology, network-on-chips (NoCs) are designed on silicon chips
to expand on-chip communications. Three-dimensional (3D) mesh-based architecture is …

Independent trees are used in building secure and/or fault-tolerant network communication
protocols. They have been investigated for different network topologies including tori. Dense …

The increasing popularity of deep neural network (DNN) applications demands high
computing power and efficient hardware accelerator architecture. DNN accelerators use a …

This paper proposes and evaluates the performance of an all-to-all broadcasting algorithm
for a 2D torus Network on Chip (NoC). The proposed algorithm uses special spanning trees …

In massively multi-core System-on-Chip (SoCs), high throughput, low delay and fault
tolerance are essential factors to fully harness the computational power offered by tens and …