Implementing Grover oracles for quantum key search on AES and LowMC

S Jaques, M Naehrig, M Roetteler, F Virdia - Advances in Cryptology …, 2020 - Springer
Grover's search algorithm gives a quantum attack against block ciphers by searching for a
key that matches a small number of plaintext-ciphertext pairs. This attack uses O (N) O (N) …

New circuit minimization techniques for smaller and faster AES SBoxes

A Maximov, P Ekdahl - IACR Transactions on Cryptographic …, 2019 - tches.iacr.org
In this paper we consider various methods and techniques to find the smallest circuit
realizing a given linear transformation on n input signals and m output signals, with a …

VLSI design of Advanced-Features AES CryptoProcessor in the framework of the European Processor Initiative

P Nannipieri, S Di Matteo, L Baldanzi… - … Transactions on Very …, 2021 - ieeexplore.ieee.org
This article presents a cryptographic hardware (HW) accelerator supporting multiple
advanced encryption standard (AES)-based block cipher modes, including the more …

Atomic-AES: A Compact Implementation of the AES Encryption/Decryption Core

S Banik, A Bogdanov, F Regazzoni - … on Cryptology in India, Kolkata, India …, 2016 - Springer
The implementation of the AES encryption core by Moradi et al. at Eurocrypt 2011 is one of
the smallest in terms of gate area. The circuit takes around 2400 gates and operates on an 8 …

Compact and efficient structure of 8-bit S-box for lightweight cryptography

B Rashidi - Integration, 2021 - Elsevier
In this paper, we design an inversion-based S-box with better hardware implementation than
the AES S-box with similar cryptographic properties. The proposed S-box computation …

Smashing the implementation records of AES S-box

A Reyhani-Masoleh, M Taha… - IACR transactions on …, 2018 - tches.iacr.org
Canright S-box has been known as the most compact S-box design since its introduction
back in CHES'05. Boyar-Peralta proposed logic-minimization heuristics that could reduce …

High throughput/gate AES hardware architectures based on datapath compression

R Ueno, S Morioka, N Miura, K Matsuda… - IEEE Transactions …, 2019 - ieeexplore.ieee.org
This article proposes highly efficient Advanced Encryption Standard (AES) hardware
architectures that support encryption and both encryption and decryption. New operation …

Securing AES designs against power analysis attacks: a survey

TB Singha, RP Palathinkal… - IEEE Internet of Things …, 2023 - ieeexplore.ieee.org
With the advent of Internet of Things (IoT), the call for hardware security has been seriously
demanding due to the risks of side-channel attacks from adversaries. Advanced encryption …

Toward more efficient DPA-resistant AES hardware architecture based on threshold implementation

R Ueno, N Homma, T Aoki - … on Constructive Side-Channel Analysis and …, 2017 - Springer
This paper presents a highly efficient AES hardware architecture resistant to differential
power analyses (DPAs) on the basis of threshold implementation (TI). In contrast to other …

A High Throughput/Gate AES Hardware Architecture by Compressing Encryption and Decryption Datapaths: —Toward Efficient CBC-Mode Implementation

R Ueno, S Morioka, N Homma, T Aoki - … Barbara, CA, USA, August 17-19 …, 2016 - Springer
This paper proposes a highly efficient AES hardware architecture that supports both
encryption and decryption for the CBC mode. Some conventional AES architectures employ …