This tutorial discusses the design and ASIC implementation of coherent optical transceivers.
Algorithmic and architectural options and tradeoffs between performance and …

We present an O(\lg\lgn)-competitive online binary search tree, improving upon the best
previous (trivial) competitive ratio of O(\lgn). This is the first major progress on Sleator and …

The improvement of file access performance is a great challenge in real-time cloud services.
In this paper, we analyze preconditions of dealing with this problem considering the aspects …

Self-testing hardware has a long tradition as a complement to manufacturing testing based
on test stimuli and response analysis. Today, it is a mature field and many complex SoCs …

This paper describes a low-power (LP) programmable generator capable of producing
pseudorandom test patterns with desired toggling levels and enhanced fault coverage …

This paper presents a novel scan-based design for test (DFT) paradigm. Compared with
conventional scan, the presented approach either significantly reduces test application time …

Failures become inevitable in DRAM devices, which is a major obstacle for scaling down the
density of cells in future DRAM technologies. These failures can be detected by specific …

This paper presents a new pseudorandom test pattern generator with preselected toggling
(PRESTO) activity. It is comprised of a linear finite state machine (a linear feedback shift …

The embedded deterministic test-based compression uses cube merging to reduce a pattern
count, the amount of test data, and test time. It gradually expands a test pattern by …

Integrated circuit (IC) testing presents complex problems that for large circuits are
exceptionally difficult to solve by traditional computing techniques. To deal with …