[图书][B] Asynchronous circuit design

CJ Myers - 2001 - books.google.com
With asynchronous circuit design becoming a powerful tool in the development of new
digital systems, circuit designers are expected to have asynchronous design skills and be …

[图书][B] Logic synthesis for asynchronous controllers and interfaces

J Cortadella, M Kishinevsky, A Kondratyev, L Lavagno… - 2012 - books.google.com
This book is the result of a long friendship, of a broad international co operation, and of a
bold dream. It is the summary of work carried out by the authors, and several other wonderful …

Relative timing [asynchronous design]

KS Stevens, R Ginosar, S Rotem - IEEE Transactions on Very …, 2003 - ieeexplore.ieee.org
Relative timing (RT) is introduced as a method for asynchronous design. Timing
requirements of a circuit are made explicit using relative timing. Timing can be directly …

On multi-enabledness in time Petri nets

H Boucheneb, D Lime, OH Roux - Application and Theory of Petri Nets and …, 2013 - Springer
We consider time Petri nets with multiple-server semantics. We first prove that this setting is
strictly more expressive, in terms of timed bisimulation, than its single-server counterpart. We …

Timed circuits: A new paradigm for high-speed design

CJ Myers, W Belluomini, K Kallpack, E Peskin… - Proceedings of the …, 2001 - dl.acm.org
In order to continue to produce circuits of increasing speeds, designers must consider
aggressive circuit design styles such as self-resetting or delayed-reset domino circuits used …

Timed state space exploration using posets

W Belluomini, CJ Myers - IEEE Transactions on Computer …, 2000 - ieeexplore.ieee.org
This paper presents a new timing analysis algorithm for efficient state space exploration
during the synthesis of timed circuits or the verification of timed systems. The source of the …

Timed circuit verification using TEL structures

W Belluomini, CJ Myers… - IEEE Transactions on …, 2001 - ieeexplore.ieee.org
Recent design examples have shown that significant performance gains are realized when
circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in …

[图书][B] Algorithms for synthesis and verification of timed circuits and systems

WA Belluomini - 1999 - search.proquest.com
In order to increase performance, circuit designers are beginning to move away from
traditional, synchronous designs based on static logic. Recent design examples have shown …

[PDF][PDF] Improved poset timing analysis in timed petri nets

EG Mercer, CJ Myers, T Yoneda - The Tenth Workshop on …, 2001 - researchgate.net
This paper presents an improved timing algorithm for the analysis of timed Petri nets that is
based on the POSET algorithm. The new algorithm reduces the number of redundant …

Partial order path technique for checking parallel timed automata

J Zhao, H Xu, X Li, T Zheng, G Zheng - … on Formal Techniques in Real-Time …, 2002 - Springer
In a parallel composition of timed automata, some transitions are independent to others.
Generally the basic method generates one successors for each of the legal permutations of …