Semiconductor device, systems and methods of manufacture
K Taekyung, KS Seol, SS Cho, S Hur… - US Patent …, 2018 - Google Patents
A semiconductor memory device includes a stack of word lines and insulating patterns. Cell
pillars extend vertically through the stack of word lines and insulating patterns with memory …
pillars extend vertically through the stack of word lines and insulating patterns with memory …
NAND boosting using dynamic ramping of word line voltages
P Rabkin, Y Dong, M Higashitani - US Patent 9,530,506, 2016 - Google Patents
Methods for improving channel boosting and reducing program disturb during programming
of memory cells within a memory array are described. The memory array may comprise a …
of memory cells within a memory array are described. The memory array may comprise a …
Pre-charge during programming for 3D memory using gate-induced drain leakage
M Dunga, Y Dong, W Ou - US Patent 8,988,937, 2015 - Google Patents
8, 107,292 B2 1/2012 Maejima 8, 199,573 B2 6/2012 Fukuzumi et al. 2009, O168533 A1 7,
2009 Park et al. 20090310425 A1 12/2009 Sim et al. 2010.0054036 A1 3/2010 Lee et al …
2009 Park et al. 20090310425 A1 12/2009 Sim et al. 2010.0054036 A1 3/2010 Lee et al …
Nonvolatile memory device and memory system including the same
SW Nam, KH Kang, J Park - US Patent 8,976,591, 2015 - Google Patents
According to example embodiments, a nonvolatile memory device includes a first and a
second NAND string. The first NAND string includes a first string selection transistor, a first …
second NAND string. The first NAND string includes a first string selection transistor, a first …
Nonvolatile memory device and worldline driving method thereof
SW Nam, YUN Sun-Min, BS Lim, Y Choi - US Patent 9,378,820, 2016 - Google Patents
According to example embodiments of inventive concepts, a nonvolatile memory device
includes a memory cell array, an address decoder, an input/output circuit, a Voltage …
includes a memory cell array, an address decoder, an input/output circuit, a Voltage …
Semiconductor memory
T Hashimoto - US Patent 9,672,918, 2017 - Google Patents
(57) ABSTRACT A semiconductor memory includes a first selection transistor and a second
selection transistor on one end of a memory string. The first selection transistor includes a …
selection transistor on one end of a memory string. The first selection transistor includes a …
Pre-charge during programming for 3D memory using gate-induced drain leakage
M Dunga, Y Dong, W Ou - US Patent 8,988,939, 2015 - Google Patents
In a programming operation of a 3D stacked non-volatile memory device, the channel of an
inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a …
inhibited NAND string is pre-charged by gate-induced drain leakage (GIDL) to achieve a …
Stacked independently contacted field effect transistor having electrically separated first and second gates
RM Hatcher, BJ Obradovic, JG Hong… - US Patent …, 2018 - Google Patents
2016-06-23 Assigned to SAMSUNG ELECTRONICS CO., LTD. reassignment SAMSUNG
ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …
ELECTRONICS CO., LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT …
Three-dimensional vertical memory comprising dice with different interconnect levels
G Zhang - US Patent 9,559,082, 2017 - Google Patents
Related US Application Data is a continuation-in-part of application No. 14/803, 104, filed on
Jul. 19, 2015, now abandoned, which is a continuation-in-part of application No. 14/636,359 …
Jul. 19, 2015, now abandoned, which is a continuation-in-part of application No. 14/636,359 …
NAND boosting using dynamic ramping of word line voltages
P Rabkin, Y Dong, M Higashitani - US Patent 10,297,329, 2019 - Google Patents
Methods for improving channel boosting and reducing program disturb during programming
of memory cells within a memory array are described. The memory array may comprise a …
of memory cells within a memory array are described. The memory array may comprise a …