Increasing dynamic variability with technology scaling has made it essential to incorporate
large design-time timing margins to ensure yield and reliable operation. Online techniques …

As dynamic variability increases with CMOS scaling, it is essential to incorporate large
design-time timing margins to ensure yield and reliable operation. Online techniques for …

Considering the variety of studies that have been reported in low‐power designing era, the
subthreshold design trend in Very Large Scale Integrated (VLSI) circuits has experienced a …

NTV is a new low power design concept for the pursuit of the highest power usage
efficiency. The characteristics for each logic family are quite different under NTV while …

In this paper, we present and solve the problem of power-delay optimal soft linear pipeline
design. The key idea is to use soft-edge flip-flops to allow time borrowing among …

In this paper, we present a technique to optimize the energy-delay product of a synchronous
linear pipeline circuit with dynamic error detection and correction capability running. The …

We present a low-overhead solution to tackle the delay increase caused by Negative Bias
Temperature Instability (NBTI), which has emerged as the most critical reliability issue in sub …

CMOS technology scaling, the process of shrinking transistor dimensions based on Moore's
law, has been the thrust behind increasingly powerful integrated circuits for over half a …

As technology scales down, timing errors are a real concern in high complexity and high
frequency integrated circuits. Process, Voltage and Temperature variations lead to large …

Design of high-performance processors has undergone a drastic change since the start of
the new millennium due to power consumption related difficulties, such as heat dissipation …