Multi-gate device and method of fabrication thereof
KC Ching, CC Wu, CF Huang, WH Hsieh… - US Patent …, 2020 - Google Patents
(57) ABSTRACT A semiconductor includes a first transistor and a second transistor. The first
transistor includes a first and a second epitaxial layer, formed of a first semiconductor …
transistor includes a first and a second epitaxial layer, formed of a first semiconductor …
Methods of forming nanosheet transistor with dielectric isolation of source-drain regions and related structure
An IC structure according to the disclosure includes: a substrate; a pair of transistor sites
positioned on the sub strate, wherein an upper surface of the substrate laterally between the …
positioned on the sub strate, wherein an upper surface of the substrate laterally between the …
Rectangular nanosheet fabrication
RM Hatcher, RC Bowen, WE Wang… - US Patent App. 14 …, 2016 - Google Patents
Exemplary embodiments provide methods for fabricating a nanosheet structure suitable for
field-effect transistor (FET) fabrication. Aspects of exemplary embodiment include selecting …
field-effect transistor (FET) fabrication. Aspects of exemplary embodiment include selecting …
Self-aligned 3-D epitaxial structures for MOS device fabrication
GA Glass, DB Aubertine, AS Murthy, G Thareja… - US Patent …, 2017 - Google Patents
2012-08-28 Assigned to INTEL CORPORATION reassignment INTEL CORPORATION
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors …
Methods of forming stressed channel regions for a FinFET semiconductor device and the resulting device
One method disclosed includes, among other things, covering the top surface and a portion
of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate …
of the sidewalls of an initial fin structure with etch stop material, forming a sacrificial gate …
Method for making nanosheet CMOS device integrating atomic layer deposition process and replacement gate structure
BB Doris, MA Guillorn, I Lauer, X Miao - US Patent 9,911,592, 2018 - Google Patents
A semiconductor device including a gate structure present on at least two suspended
channel structures, and a composite spacer present on sidewalls of the gate structure. The …
channel structures, and a composite spacer present on sidewalls of the gate structure. The …
Co-integration of silicon and silicon-germanium channels for nanosheet devices
MA Guillorn, I Lauer, NJ Loubet - US Patent 9,755,017, 2017 - Google Patents
Nanosheet semiconductor devices and methods of forming the same include forming a first
nanosheet stack in a first device region with layers of a first channel material and layers of a …
nanosheet stack in a first device region with layers of a first channel material and layers of a …
Nanosheet field-effect transistor with full dielectric isolation
Methods for forming a structure for a nanosheet field-effect transistor. A body feature is
formed that includes a plurality of nanosheet channel layers and a plurality of first sacrificial …
formed that includes a plurality of nanosheet channel layers and a plurality of first sacrificial …
Integrated circuits with nanowires and methods of manufacturing the same
Integrated circuits and methods for producing the same are provided. A method for
producing an integrated circuit includes forming a layered fin overlying a Substrate, where …
producing an integrated circuit includes forming a layered fin overlying a Substrate, where …
Silicon and silicon germanium nanowire formation
Among other things, one or semiconductor arrangements, and techniques for forming Such
semiconductor arrange ments are provided. For example, one or more silicon and silicon …
semiconductor arrange ments are provided. For example, one or more silicon and silicon …