A survey on pipelined FFT hardware architectures
M Garrido - Journal of Signal Processing Systems, 2022 - Springer
The field of pipelined FFT hardware architectures has been studied during the last 50 years.
This paper is a survey that includes the main advances in the field related to architectures for …
This paper is a survey that includes the main advances in the field related to architectures for …
BASALISC: Programmable asynchronous hardware accelerator for BGV fully homomorphic encryption
Fully Homomorphic Encryption (FHE) allows for secure computation on encrypted data. We
present BASALISC, an architecture family of hardware accelerators that aims to substantially …
present BASALISC, an architecture family of hardware accelerators that aims to substantially …
Energy-efficient fast Fourier transform for real-valued applications
C Eleftheriadis, G Karakonstantis - IEEE Transactions on …, 2022 - ieeexplore.ieee.org
This brief presents a new energy efficient Fast-Fourier Transform (FFT) architecture for real-
valued applications. The proposed architecture decimates the FFT in time domain with bit …
valued applications. The proposed architecture decimates the FFT in time domain with bit …
Advanced quantization schemes to increase accuracy, reduce area, and lower power consumption in FFT architectures
M Garrido, VM Bautista, A Portas… - IEEE Transactions on …, 2024 - ieeexplore.ieee.org
This paper explores new advanced quantization schemes for fast Fourier transform (FFT)
architectures. In previous works, FFT quantization has been treated theoretically or with the …
architectures. In previous works, FFT quantization has been treated theoretically or with the …
Feedforward FFT hardware architectures based on rotator allocation
M Garrido, SJ Huang, SG Chen - IEEE Transactions on Circuits …, 2017 - ieeexplore.ieee.org
In this paper, we present new feedforward FFT hardware architectures based on rotator
allocation. The rotator allocation approach consists in distributing the rotations of the FFT in …
allocation. The rotator allocation approach consists in distributing the rotations of the FFT in …
Low-Latency 64-Parallel 4096-Point Memory-Based FFT for 6G
This paper presents a novel 64-parallel 4096-point radix-2 memory-based fast Fourier
transform (FFT) architecture for 6G. This approach is the first one to use 64 parallel branches …
transform (FFT) architecture for 6G. This approach is the first one to use 64 parallel branches …
An ultralow power system on chip for automatic sleep staging
SA Imtiaz, Z Jiang… - IEEE Journal of Solid …, 2017 - ieeexplore.ieee.org
This paper presents an ultralow power system on chip (SoC) for automatic sleep staging
using a single electroencephalogram (EEG) channel. The system integrates an analog front …
using a single electroencephalogram (EEG) channel. The system integrates an analog front …
Hardware architectures for the fast Fourier transform
The fast Fourier transform (FFT) is a widely used algorithm in signal processing applications.
FFT hardware architectures are designed to meet the requirements of the most demanding …
FFT hardware architectures are designed to meet the requirements of the most demanding …
A 1 million-point FFT on a single FPGA
In this paper, we present the first implementation of a 1 million-point fast Fourier transform
(FFT) completely integrated on a single field-programmable gate array (FPGA), without the …
(FFT) completely integrated on a single field-programmable gate array (FPGA), without the …
A non-blind deconvolution semi pipelined approach to understand text in blurry natural images for edge intelligence
Text understanding from natural scene images has progressively gained much interest in
computer vision due to the frequent emergence of handheld or wearable devices …
computer vision due to the frequent emergence of handheld or wearable devices …