(51) Int. Cl. A charge trapping floating gate is described with asymmetric GIC I6/06(2006.01)
tunneling barriers. The memory cell includes a source region HOIL 29/788(2006.01) and a …

Methods of operating non-volatile memory devices are described. The memory devices
comprise memory cells having an n-type semiconductor substrate and p-type source and …

Memory cells comprising: a semiconductor substrate having a source region and a drain
region disposed below a surface of the substrate and separated by a channel region; a …

High-k dielectrics have been intensively investigated during the last decade, and their
performance as a gate dielectric has been improved to the level of conventional SiO 2 …

(57) ABSTRACT A vertical channel memory including a substrate, a channel, a multi-layer
structure, a gate, a first terminal and a second terminal is provided. The channel protrudes …

A bandgap engineered SONOS device structure for design with various AND architectures.
The BE-SONOS device structure comprises a spacer oxide disposed between a control gate …

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5,286,994 A 2f1994 Ozawa et al. 2007, 0138539 A1 6, 2007 Wu et al. 5,319,229 A 6/1994 …

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Jan. 3, 2006, now Pat. No. 7,315,474, application No.(74) Attorney, Agent, or Firm—
McClure, Qualey & 12/056,489, which is a continuation-in-part of Rodack, LLP application …

A memory device includes an array of strings of memory cells. The device includes a
plurality of stacks of conductive strips separated by insulating material, including at least a …