Mitigation of radiation effects in SRAM-based FPGAs for space applications

F Siegle, T Vladimirova, J Ilstad, O Emam - ACM Computing Surveys …, 2015 - dl.acm.org
The use of static random access memory (SRAM)-based field programmable gate arrays
(FPGAs) in harsh radiation environments has grown in recent years. These types of …

VTR 8: High-performance CAD and customizable FPGA architecture modelling

KE Murray, O Petelin, S Zhong, JM Wang… - ACM Transactions on …, 2020 - dl.acm.org
Developing Field-programmable Gate Array (FPGA) architectures is challenging due to the
competing requirements of various application domains and changing manufacturing …

VTR 7.0: Next generation architecture and CAD system for FPGAs

J Luu, J Goeders, M Wainberg, A Somerville… - ACM Transactions on …, 2014 - dl.acm.org
Exploring architectures for large, modern FPGAs requires sophisticated software that can
model and target hypothetical devices. Furthermore, research into new CAD algorithms …

Reconfigurable computing architectures

R Tessier, K Pocek, A DeHon - Proceedings of the IEEE, 2015 - ieeexplore.ieee.org
Reconfigurable architectures can bring unique capabilities to computational tasks. They
offer the performance and energy efficiency of hardware with the flexibility of software. In …

Recent advances in FPGA reverse engineering

H Yu, H Lee, S Lee, Y Kim, HM Lee - Electronics, 2018 - mdpi.com
In this paper, we review recent advances in reverse engineering with an emphasis on FPGA
devices and experimentally verified advantages and limitations of reverse engineering tools …

A survey of hardware Trojan threat and defense

H Li, Q Liu, J Zhang - Integration, 2016 - Elsevier
Abstract Hardware Trojans (HTs) can be implanted in security-weak parts of a chip with
various means to steal the internal sensitive data or modify original functionality, which may …

Rapidwright: Enabling custom crafted implementations for fpgas

C Lavin, A Kaviani - 2018 IEEE 26th Annual International …, 2018 - ieeexplore.ieee.org
FPGA application size is rapidly growing by reuse and replication. Achieved quality of
results (QoR) of these large designs is often much lower than what could be realized with …

Yosys+ nextpnr: an open source framework from verilog to bitstream for commercial fpgas

D Shah, E Hung, C Wolf, S Bazanski… - 2019 IEEE 27th …, 2019 - ieeexplore.ieee.org
This paper introduces a fully free and open source software (FOSS) architecture-neutral
FPGA framework comprising of Yosys for Verilog synthesis, and nextpnr for placement …

Go ahead: A partial reconfiguration framework

C Beckhoff, D Koch, J Torresen - 2012 IEEE 20th International …, 2012 - ieeexplore.ieee.org
Exploiting the benefits of partial run-time reconfiguration requires efficient tools. In this
paper, we introduce the tool Go Ahead that is able to implement run-time reconfigurable …

Timing-driven titan: Enabling large benchmarks and exploring the gap between academic and commercial CAD

KE Murray, S Whitty, S Liu, J Luu, V Betz - ACM Transactions on …, 2015 - dl.acm.org
Benchmarks play a key role in Field-Programmable Gate Array (FPGA) architecture and
CAD research, enabling the quantitative comparison of tools and architectures. It is …