Physically unclonable functions using two-level finite state machine

V Vijay, K Chaitanya, CS Pittala… - Journal of VLSI …, 2022 - vlsijournal.com
The usage of physically unclonable functions is for authentications, identification
applications, signature generation, IC metering, and cryptographic key generation …

Design of unbalanced ternary logic gates and arithmetic circuits

V Vijay, CS Pittala, KC Koteshwaramma… - Journal of VLSI …, 2022 - vlsijournal.com
The design of ternary Logic gates–Ternary NAND, Ternary NOR and Standard Ternary
Inverter based on the 18nm FinFET technology is proposed. The Ternary logic systems …

Realısatıon of Performance Optımısed 32-Bıt Vedıc Multıplıer

J Sravana, KS Indrani, M Saranya, PS Kiran… - Journal of VLSI …, 2022 - vlsijournal.com
This paper demonstrates the improved adaptation of the Vedic Multiplier using the Vedic
standards, which includes old sutras. In this paper, current and proposed model are …

QCA Based Universal Shift Register using 2 to 1 Mux and D flip-flop

S Sushma, S Swathi, V Bindusree… - … on Advances in …, 2021 - ieeexplore.ieee.org
A Quantum-dot cellular automaton (QCA) represents a modern technology for implementing
small-sized circuits with high-performance, low-power consumption and various …

ASIC Implementation of An Effective Reversible R2B Fft for 5G Technology Using Reversible Logic

KC Koteshwaramma, V Vijay, V Bindusree… - Journal of VLSI …, 2022 - vlsijournal.com
In recent times, 5G technology is an emerging advancement in the communication system.
Because of its improved properties such as bandwidth, speed, connectivity etc., it has …

Design of carry select adder using logic optimization technique

M Sreevani, S Lakshmanachari… - … on Advances in …, 2021 - ieeexplore.ieee.org
Carry Select Adder (CSLA) is an essentially utilized adder on account of its higher
computational speed. CSLA is utilized in the space of incorporation frameworks. This paper …

Pipelined Distributive Arithmetic-based FIR Filter Using Carry Save and Ripple Carry Adder

M Saritha, C Radhika, MN Reddy… - … and Industry 4.0 …, 2021 - ieeexplore.ieee.org
FIR filter bank play a vital role in any signal processing systems. The FIR filter is used to
implement any frequency response digitally. Usually, the FIR filters contain multipliers …

Design and performance analysis of low power and energy-efficient vedic multipliers

S Shaik, S Kanapala, V Vijay, CS Pittala - International Journal of System …, 2023 - Springer
This paper explores low-power and energy-efficient multi-bit Vedic Multiplier (VM)
architectures at a supply voltage as low as 0.6 V. Energy efficient architectures are a …

Implementation of fundamental modules using quantum dot cellular automata

V Vijay, CS Pittala, AU Rani, S Shaik… - Journal of VLSI …, 2022 - vlsijournal.com
This paper aims to design logic gates and flip flops using QCA. This paper demonstrates the
implementation of logic gates.(AND GATE, OR GATE, NOR GATE, NOT GATE, EXORGATE …

Implementation of An Energy-Efficient Binary Square Rooter Using Reversible Logic By Applying The Non-Restoring Algorithm

S Swathi, S Sushma, V Bindusree… - … and Industry 4.0 …, 2021 - ieeexplore.ieee.org
Calculation of square root will be an essential mathematical operation that will have broad
applications. In Hardware, the square root will be designed in order to gain power which will …