A fractional-N frequency synthesizer inherently exhibits spurs by virtue of the fact that its
output frequency is not an integer multiple of its reference frequency. Until recently, it …

The fundamentals and state of the art in fractional-N phase-locked-loop (PLL)-based
frequency synthesis are reviewed. Particular emphasis is placed on delta-sigma fractional-N …

The book Computer Applications in Engineering and Management is about computer
applications in management, electrical engineering, electronics engineering, and civil …

A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-
antenna transceivers is presented. The system is modular with one phase locked loop (PLL) …

This book describes several Digital Delta-Sigma Modulator (DDSM) architectures, including
multi stage noise shaping (MASH), error feedback modulator (EFM) and single quantizer …

For multistage noise-shaping (MASH) delta-sigma modulation, this paper presents a new
structure that is free of spurs for all input values. The proposed MASH structure cascades …

Fractional-N frequency synthesizers based on phase-locked loops exhibit spurious tones
(spurs) that result from interactions between the accumulated output of the divider controller …

The digital multistage-noise-shaping (MASH) ΣΔ modulators used in fractional frequency
synthesizers are prone to spur tone generation in their output spectrum. In this paper, the …

This paper presents the design and verification of a proposed 30-GHz power-efficient phase-
locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a …

Digital-to-time converters (DTC's) used in fractional-phase locked loops (PLL's) aim to zero
the quantization error (QE) introduced by the divider controller in order to recover integer …