Comprehensive study of 1-bit full adder cells: review, performance comparison and scalability analysis

M Hasan, AH Siddique, AH Mondol, M Hossain… - SN Applied …, 2021 - Springer
Full Adder (FA) circuits are integral components in the design of Arithmetic Logic Units
(ALUs) of modern computing systems. Recently, there have been massive research interests …

Low-power and fast full adder by exploring new XOR and XNOR gates

H Naseri, S Timarchi - IEEE transactions on very large scale …, 2018 - ieeexplore.ieee.org
In this paper, novel circuits for XOR/XNOR and simultaneous XOR-XNOR functions are
proposed. The proposed circuits are highly optimized in terms of the power consumption …

A novel hybrid full adder based on gate diffusion input technique, transmission gate and static CMOS logic

M Hasan, UK Saha, A Sorwar… - 2019 10th …, 2019 - ieeexplore.ieee.org
This research proposes a hybrid Full Adder (FA) cell using a combination of Gate Diffusion
Input (GDI) technique, Transmission Gate (TG) and conventional Static CMOS (C-CMOS) …

Design analysis of XOR (4T) based low voltage CMOS full adder circuit

S Wairya, G Singh, RK Nagaria… - 2011 Nirma University …, 2011 - ieeexplore.ieee.org
This paper presents a comparative study of highspeed, low-power and low voltage full adder
circuits. Our approach is based on XOR-XNOR (4T) design full adder circuits combined in a …

Performance analysis of high speed hybrid CMOS full adder circuits for low voltage VLSI design

S Wairya, RK Nagaria, S Tiwari - VLSI Design, 2012 - Wiley Online Library
This paper presents a comparative study of high‐speed and low‐voltage full adder circuits.
Our approach is based on hybrid design full adder circuits combined in a single unit. A high …

[PDF][PDF] Comparative performance analysis of XORXNOR function based high-speed CMOS full adder circuits for low voltage VLSI design

S Wairya, RK Nagaria, S Tiwari - International Journal of VLSI …, 2012 - academia.edu
This paper presents comparative study of high-speed, low-power and low voltage full adder
circuits. Our approach is based on XOR-XNOR design full adder circuits in a single unit. A …

[PDF][PDF] New design methodologies for high-speed mixed-mode CMOS full adder circuits

S Wairya, RK Nagaria, S Tiwari - International Journal of VLSI design …, 2011 - academia.edu
This paper presents the design of high-speed full adder circuits using a new CMOS mixed
mode logic family. The objective of this work is to present a new full adder design circuits …

Fast and high-performing 1-bit full adder circuit based on input switching activity patterns and gate diffusion input technique

I Hussain, S Chaudhury - Circuits, Systems, and Signal Processing, 2021 - Springer
For computational arithmetic, a full adder is the primary logic units in VLSI applications. A
new full adder circuit design has been presented in this article which is based on input …

Ultra low-power high-speed single-bit hybrid full adder circuit

M Kumar, RK Baghel - 2017 8th International Conference on …, 2017 - ieeexplore.ieee.org
In this paper a low power hybrid 1-bit full adder circuit is designed and extended for 4 bit
ripple carry adder (RCA). A new XNOR logic is designed using complimentary-metal-oxide …

Novel Design of Ripple Carry Adder using High Speed 12T Hybrid MOS Transistors

D Venkat, T Mendez, R Samanth… - Journal of Physics …, 2023 - iopscience.iop.org
This paper designs and extends a high speed full adder using 12 MOS Transistors to a
ripple carry adder (RCA). The proposed design reduces delay and is effective for Power …