An energy and area efficient 4: 2 compressor based on FinFETs

A Arasteh, MH Moaiyeri, MR Taheri, K Navi… - Integration, 2018 - Elsevier
In this paper, a new energy and area efficient 4: 2 compressor is presented. The proposed
compressor is designed efficiently based on multiplexer and XOR modules. The efficiency of …

Novel CNFET ternary circuit techniques for high‐performance and energy‐efficient design

S Tabrizchi, MR Taheri, K Navi… - IET Circuits, Devices & …, 2019 - Wiley Online Library
Here, the authors propose a new family of ternary circuits for a general design perspective.
Besides presenting an efficient ternary logical circuit approaches, the focus of this study is …

Method for designing ternary adder cells based on CNFETs

S Tabrizchi, A Panahi, F Sharifi, K Navi… - IET Circuits, Devices …, 2017 - Wiley Online Library
Recently multiple valued logic has attracted the attention of digital system designers.
Scalable threshold voltage values of carbon nanotube field‐effect transistors (CNFETs) can …

Robust coplanar full adder based on novel inverter in quantum cellular automata

M Zahmatkesh, S Tabrizchi, S Mohammadyan… - International Journal of …, 2019 - Springer
Quantum dot cellular automata (QCA) is one of the nano-scale computing paradigms which
promises high speed and ultra-low power consumption. Since the one-bit full adder is a …

An efficient counter-based Wallace-tree multiplier with a hybrid full adder core for image blending

A Sadeghi, N Shiri, M Rafiee, M Tahghigh - Frontiers of Information …, 2022 - Springer
We present a new counter-based Wallace-tree (CBW) 8× 8 multiplier. The multiplier's
counters are implemented with a new hybrid full adder (FA) cell, which is based on the …

An optimization of low power 4-bit PAL FIR filter using adiabatic techniques

A Rai - Sādhanā, 2023 - Springer
This paper proposes a 4-bit FIR filter useful in communication and many application of
Digital Signal Processing (DSP) using fully adiabatic technology PAL, which reduces all …

Investigation of CNTFET based energy efficient fast SRAM cells for edge AI devices

Y Alekhya, U Nanda - Silicon, 2022 - Springer
A novel reduced power with enhanced speed (RPES) technique for Static Random Access
Memory (SRAM) topologies using Carbon Nano Tube Field Effect Transistors (CNTFETs) …

Design and evaluation of a 5-input majority gate-based content-addressable memory cell in quantum-dot cellular automata

MB Khosroshahy, MH Moaiyeri… - 2017 19th international …, 2017 - ieeexplore.ieee.org
Quantum-dot cellular automata (QCA) has been introduced as an emerging nanotechnology
for circuit design. This technology is one of the best alternatives to the CMOS circuits. In QCA …

A Novel Current Mode Approximate Multiplier Scheme Based on 4: 2 and 5: 2 Compressors with Low Power Consumption and High Speed in CNTFET Technology

P Foroutan, K Navi - Circuits, Systems, and Signal Processing, 2024 - Springer
Recent developments in multiplication circuits with fewer transistors, higher speed, and
reduced energy consumption are lowering hardware costs. Approximate multiplication is …

[PDF][PDF] Low power architecture of logic gates using adiabatic techniques

M Sanadhya, DK Sharma - Indones J Electr Eng Comput Sci, 2022 - academia.edu
The growing significance of portable systems to limit power consumption in ultra-large-scale-
integration chips of very high density, has recently led to rapid and inventive progresses in …