Distributed test data compression refers to the scenario where each logic block in a design
has its own decompression logic and compact set of compressed tests. A static test …

In a design that consists of several logic blocks, each logic block may be tested separately
using its own compressed test set and on-chip decompression logic. The decompression …

Continued advances in process technology have led to a relentless increase in the design
complexity of integrated circuits (ICs). In order to meet the increasing demand of low …

Iterative synthesis consists of local design modifications to improve design parameters or
correct design errors. Incremental test generation was suggested for evaluating the effects of …

Testing large circuits requires compression of test patterns before transferring them to the
tested circuit and decompression on board. The compression and decompression …

With increasing system complexity, security, stringent runtime requirements for functional
safety, and cost constraints of a mass market, the reliable and secure operation of …

Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our
observation, the test patterns generated by ATPG tools in test compression mode still …

Dynamic test compaction techniques are used during test generation to ensure that each
test detects as many faults as possible, resulting in the smallest possible number of tests. As …

Minimizing the testing cost is crucial in the context of the design for test (DFT) flow. In our
observation, the test patterns generated by commercial ATPG tools in test compression …

Compaction of scan-based test sets is important for reducing the test application time and
test data volume. For a circuit with K flip-flops in its longest scan chain, a conventional single …