A dynamic power-efficient 4 GS/s CMOS comparator

MA Dehkordi, M Dousti, SM Mirsanei… - AEU-International Journal …, 2023 - Elsevier
This paper proposes a mid-stage latch circuit to be employed in a high-speed comparator.
The advantages of the proposed circuit are low kickback noise and offset. Moreover, low …

Low-power high-speed CMOS double tail dynamic comparator using self-biased amplification stage and novel latch stage

AK Dubey, RK Nagaria - Analog Integrated Circuits and Signal Processing, 2019 - Springer
This paper presents a low voltage double-tail dynamic comparator (DTDC) for fast and
power-efficient data conversion. The amplification stage of the proposed DTDC is designed …

A low-power high-resolution dynamic voltage comparator with input signal dependent power down technique

A Gupta, A Singh, A Agarwal - AEU-International Journal of Electronics and …, 2021 - Elsevier
A high-resolution dynamic voltage comparator with an input signal dependent power down
technique for low power applications is presented here. Without affecting the resolution, a …

A 0.2-V 1.2 nW 1-KS/s SAR ADC with a novel comparator structure for biomedical applications

M Vafaei, MR Hosseini, E Abiri, MR Salehi - Integration, 2023 - Elsevier
In this paper, a modified successive-approximation-register analog-to-digital converter (SAR
ADC) with a novel low power dynamic comparator at 0.2 V supply voltage is presented. The …

An energy-efficient, 6 GS/s dynamic comparator in 90 nm CMOS technology

M Amirkhan Dehkordi, M Dolatshahi - Analog integrated circuits and signal …, 2019 - Springer
In this paper, a two-stage dynamic comparator circuit is proposed, which considerably
reduces the power consumption as well as the power-delay product parameter, while …

A low-power low-offset charge-sharing technique for double-tail comparators

A Khorami, R Saeidi, M Sachdev - Microelectronics Journal, 2020 - Elsevier
A charge sharing technique for high-speed double-tail comparators is presented. This
technique is applied to the pre-amplifier stage of the dynamic comparators so that the …

A low-power 8-bit 1-MS/s single-ended SAR ADC in 130-nm CMOS for medical devices

DM Ellaithy - Journal of Electrical Systems and Information …, 2024 - Springer
Rapid advancements in micro-machining and microelectronics over the last few years have
accelerated the growth of implanted medical devices that greatly improve a person's life …

Design and Analysis of a Power-Efficient Dynamic Comparator with an Improved Transconductance in Ultra-low Power SAR ADC Applications

ZM Moghadam, MR Salehi, SR Nashta… - Circuits, Systems, and …, 2024 - Springer
This paper presents an ultra-low power comparator with minimum delay and low offset, used
in successive approximation register analog-to-digital converters (SAR ADCs) for …

Thermal Performance of Dynamic Rail to Rail Voltage Comparators Designed Using 16nm Technology with a VDD of 0.7 V

K Shreya, N Fatima, K Samanvitha… - 2022 IEEE …, 2022 - ieeexplore.ieee.org
This article critically studies the role of operating temperature (T) on the speed & power
characteristics of dynamic rail to rail voltage comparators implemented using 16 nm CMOS …

Design of 150‐μV input‐referred voltage 1‐GHz comparison frequency dual offset cancelation comparator for pH biomarker system‐on‐chip

WC Lin, MC Chang, CH Liao - International Journal of Circuit …, 2022 - Wiley Online Library
The highlight of in vivo or ex vivo measurement to monitor the pH value from blood or saliva
is emerging in these years since changes in pH suggest that hidden diseases are about to …