Thermo-mechanical reliability of glass substrate and Through Glass Vias (TGV): A comprehensive review
The evolution of electronic packaging technology towards the adoption of glass substrates
marks a significant advancement in overcoming the constraints posed by traditional organic …
marks a significant advancement in overcoming the constraints posed by traditional organic …
Design, fabrication, and characterization of ultrathin 3-D glass interposers with through-package-vias at same pitch as TSVs in silicon
V Sukumaran, G Kumar… - IEEE Transactions …, 2014 - ieeexplore.ieee.org
A double-sided and ultrathin 3-D glass interposer with through package vias (TPVs) at same
pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a …
pitch as through silicon vias (TSVs) in silicon interposers is developed to provide a …
Large-scale 3D chips: Challenges and solutions for design automation, testing, and trustworthy integration
Three-dimensional (3D) integration of electronic chips has been advocated by both industry
and academia for many years. It is acknowledged as one of the most promising approaches …
and academia for many years. It is acknowledged as one of the most promising approaches …
Interposer technologies for high-performance applications
This paper explores the current state of the art in silicon, organic, and glass interposer
technologies and their high-performance applications. Issues and challenges broadly …
technologies and their high-performance applications. Issues and challenges broadly …
Latency, bandwidth and power benefits of the superchips integration scheme
In this paper, we describe the performance and power benefits of our Fine Pitch integration
scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal …
scheme on a Silicon Interconnect Fabric (Si IF). Here we propose a Simple Universal …
Three-dimensional integrated circuit which incorporates a glass interposer and method for fabricating the same
YA Chen, YJ Lu, WP Thomas III - US Patent 9,082,764, 2015 - Google Patents
A three-dimensional integrated circuit (3D-IC) which incorporates a glass interposer and a
method for fabricating the three-dimensional integrated circuit (3D-IC) with the glass …
method for fabricating the three-dimensional integrated circuit (3D-IC) with the glass …
Measurement and analysis of a high-speed TSV channel
Using high-speed through-silicon via (TSV) channels is a potential means of utilizing 3-D
interconnections to realize considerable high-bandwidth throughput in vertically stacked and …
interconnections to realize considerable high-bandwidth throughput in vertically stacked and …
High-efficiency PCB-and package-level wireless power transfer interconnection scheme using magnetic field resonance coupling
As technology develops, the number of chips increases while the thickness of mobile
products continuously decreases, which leads to the need for high-density packaging …
products continuously decreases, which leads to the need for high-density packaging …
Asymmetric wafer-level polyimide and Cu/Sn hybrid bonding for 3-D heterogeneous integration
CH Lu, SY Jhu, CP Chen, BL Tsai… - IEEE Transactions on …, 2019 - ieeexplore.ieee.org
A low-temperature wafer-level polyimide/metal asymmetric hybrid bonding structure using
Cu/Sn metal and low-curing temperature polyimide is proposed in this paper. The Cu/Sn …
Cu/Sn metal and low-curing temperature polyimide is proposed in this paper. The Cu/Sn …
Compact transient thermal model of microfluidically cooled three-dimensional stacked chips with pin-fin enhanced microgap
Abstract Three-dimensional (3D) stacked integrated circuit (SIC) chips are one of the most
promising technologies to achieve compact, high-performance, and energy-efficient …
promising technologies to achieve compact, high-performance, and energy-efficient …