Within-die delay variability in 90nm FPGAs and beyond

P Sedcole, PYK Cheung - 2006 IEEE International Conference …, 2006 - ieeexplore.ieee.org
Semiconductor scaling causes increasing and unavoidable within-die parametric variability.
This paper describes accurate measurement techniques for characterising both systematic …

Visualizing cyber attacks using IP matrix

H Koike, K Ohno, K Koizumi - IEEE Workshop on Visualization …, 2005 - ieeexplore.ieee.org
An Internet cyber threat monitoring system detects cyber threats using network sensors
deployed at particular points on the Internet, statistically analyzes the time of attack, source …

BIST-based delay-fault testing in FPGAs

M Abramovici, CE Stroud - Journal of electronic testing, 2003 - Springer
We present the first delay-fault testing approach for Field Programmable Gate Arrays
(FPGAs), applicable for on-line testing as well as for off-line manufacturing and system-level …

Application-dependent testing of FPGAs

M Tahoori - IEEE Transactions on Very Large Scale Integration …, 2006 - ieeexplore.ieee.org
Testing techniques for interconnect and logic resources of an arbitrary design implemented
into a field-programmable gate array (FPGA) are presented. The target fault list includes all …

Testing and diagnosis of interconnect faults in cluster-based FPGA architectures

IG Harris, R Tessier - … on Computer-Aided Design of Integrated …, 2002 - ieeexplore.ieee.org
As IC densities are increasing, cluster-based field programmable gate arrays (FPGA)
architectures are becoming the architecture of choice for major FPGA manufacturers. A …

Measure twice and cut once: Robust dynamic voltage scaling for FPGAs

I Ahmed, S Zhao, O Trescases… - 2016 26th International …, 2016 - ieeexplore.ieee.org
Although dynamic voltage scaling (DVS) is a popular power reduction solution that has been
widely used by processors and ASICs, it is still not commercially adopted by FPGAs. A …

[PDF][PDF] FPGA Interconnect Delay Fault Testing.

E Chmelar - ITC, 2003 - masters.donntu.ru
The interconnection network consumes the majority of die area in an FPGA. Presented is a
scalable manufacturing test method for all SRAM-based FPGAs, able to detect multiple …

Automatic application-specific calibration to enable dynamic voltage scaling in FPGAs

I Ahmed, S Zhao, O Trescases… - IEEE Transactions on …, 2018 - ieeexplore.ieee.org
Dynamic voltage scaling (DVS) is one of the most effective ways to reduce integrated circuit
power. However, the programmability of field programmable gate arrays (FPGAs) means …

Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis

P Sedcole, PYK Cheung - Proceedings of the 2007 ACM/SIGDA 15th …, 2007 - dl.acm.org
Variations in the semiconductor fabrication process results in variability in parameters
between transistors on the same die, a problem exacerbated by lithographic scaling. The re …

Design-specific path delay testing in lookup-table-based FPGAs

PR Menon, W Xu, R Tessier - IEEE Transactions on Computer …, 2006 - ieeexplore.ieee.org
Due to the increased use of field-programmable gate arrays (FPGAs) in production circuits
with high reliability requirements, the design-specific testing of FPGAs has become an …