This paper presents a novel ECG classification algorithm for inclusion as part of real-time
cardiac monitoring systems in ultra low-power wearable devices. The proposed solution is …

Routing algorithm design for on-chip networks (OCNs) has become increasingly challenging
due to high levels of integration and complexity of modern systems-on-chip (SoCs). The …

In this paper, a packet switch architecture for mesh-connected multiprocessors based on the
use of a set of input FIFO buffers and an output register matrix controlled by a novel …

Synchronous dataflow (SDF) graphs are often the computational model of choice for
specification, analysis, and automated synthesis of parallel streaming kernels targeting …

An important subset of streaming applications can be synthesized from statically-analyzable
synchronous dataflow (SDF) models. The software synthesis process typically implements …

Continuation of Moore's law and advances in fabrication technologies have enabled
development of digital computing platforms that contain many processor cores. Such chip …