Single work function enablement for silicon nanowire device
G Mulfinger, S Beasor, T McArdle - US Patent App. 15/869,325, 2019 - Google Patents
A method of forming nanosheet and nanowire transistors includes the formation of
alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si). The silicon …
alternating epitaxial layers of silicon germanium (SiGe) and silicon (Si). The silicon …
Replacement metal gate patterning for nanosheet devices
This disclosure relates to a method of replacement metal gate patterning for nanosheet
devices including: forming a first and a second nanosheet stack on a substrate, the first and …
devices including: forming a first and a second nanosheet stack on a substrate, the first and …
Patterning method for nanosheet transistors
OK Injo, B Pranatharthiharan, W Wang… - US Patent …, 2020 - Google Patents
(57) ABSTRACT A semiconductor device includes a first type nanosheet device having a
first plurality of nanosheet portions alter nately stacked with a first plurality of work function …
first plurality of nanosheet portions alter nately stacked with a first plurality of work function …
Gate-all-around FETs having uniform threshold voltage
(57) ABSTRACT A technique relates to a semiconductor device. An N-type field effect
transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work …
transistor (NFET) and a P-type field effect transistor (PFET) each include an inner work …
Gate metal patterning to avoid gate stack attack due to excessive wet etching
J Wang, A Reznicek, S Mochizuki, J Rubin - US Patent 10,573,521, 2020 - Google Patents
(57) ABSTRACT A method of forming gate structures to a nanosheet device that includes
forming at least two stacks of nanosheets, wherein each nanosheet includes a channel …
forming at least two stacks of nanosheets, wherein each nanosheet includes a channel …
Vertical stacked nanosheet CMOS transistors with different work function metals
K Cheng, J Li, R Xie, C Park - US Patent 11,158,544, 2021 - Google Patents
(57) ABSTRACT A method for forming a semiconductor device includes forming a structure
having at least a first nanosheet stack for a first device, a second nanosheet stack for a …
having at least a first nanosheet stack for a first device, a second nanosheet stack for a …
Multi-threshold voltage gate-all-around transistors
(57) ABSTRACT A method for forming a semiconductor device structure includes removing a
portion of a first dielectric layer sur rounding each of a plurality of channel layers of at least a …
portion of a first dielectric layer sur rounding each of a plurality of channel layers of at least a …
Multi-threshold voltage gate-all-around field-effect transistor devices with common gates
Devices and methods are provided to fabricate multi-thresh old voltage gate-all-around field-
effect transistor devices (eg, nanosheet field-effect transistor devices) wherein threshold …
effect transistor devices (eg, nanosheet field-effect transistor devices) wherein threshold …
Nanosheet bottom isolation and source or drain epitaxial growth
Embodiments of the present invention are directed to a method that prevents punch-through
of a bottom isolation layer and improves the quality of the source/drain epitaxial growth in a …
of a bottom isolation layer and improves the quality of the source/drain epitaxial growth in a …
Multiple dielectrics for gate-all-around transistors
(57) ABSTRACT A method is presented for attaining different gate dielectric thicknesses
across a plurality of field effect transistor (FET) devices. The method includes forming …
across a plurality of field effect transistor (FET) devices. The method includes forming …