An automated method and System is disclosed to determine an Integrated Circuit (IC)
package interconnect routing using a mathematical topological Solution. A global topo …

BACKGROUND As designers strive to improve the capabilities of new ICs, minimization of
circuit size continues to be an underlying goal. Recent developments in IC design have …

В топологическом подходе к трассировке печатных плат возникает задача вычисления
пути (формы) проводника по его топологическому пути. Предложен алгоритм …

This paper presents a new methodology for routing design in multi-chip IC packages for
reducing design time while attaining a layer efficiency comparable to hand crafted design. In …

There is a problem to calculate the path (shape) of a wire by its topological path in the
topological approach to the wire routing. An algorithm which calculates the minimum length …

Today's submicron technologies increase the IC sensitivity to the physical manufacturing
defects, which results in poor initial product yield. It is well known that IC layout can be made …

As the technology scales advancing into the nanometer region, the concept of yield has
become an increasingly important design metric. To reduce the yield loss caused by local …

Curvilinear routing has been a long standing problem in layout design. Several algorithms
have been proposed based on real numbers but none of them considers the numerical error …