A 65-nm CMOS fully integrated transceiver module for 60-GHz wireless HD applications
A Siligaris, O Richard, B Martineau… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
A fully integrated WirelessHD compatible 60-GHz transceiver module in 65-nm CMOS
process is presented, covering the four standard channels. The silicon die is flip-chipped on …
process is presented, covering the four standard channels. The silicon die is flip-chipped on …
A 21–48 GHz subharmonic injection-locked fractional-N frequency synthesizer for multiband point-to-point backhaul communications
This paper presents a mm-wave subharmonic injection-locked (SHIL) fractional-N frequency
synthesizer for wireless multiband point-to-point backhaul communications. The SHIL …
synthesizer for wireless multiband point-to-point backhaul communications. The SHIL …
A 28-nm FD-SOI 115-fs jitter PLL-based LO system for 24–30-GHz sliding-IF 5G transceivers
S Ek, T Påhlsson, C Elgaard, A Carlsson… - IEEE Journal of Solid …, 2018 - ieeexplore.ieee.org
A system for local oscillator (LO) signal generation in 5G millimeter-wave (mmW) multi-
antenna transceivers is presented. The system is modular with one phase locked loop (PLL) …
antenna transceivers is presented. The system is modular with one phase locked loop (PLL) …
A linearized, low-phase-noise VCO-based 25-GHz PLL with autonomic biasing
This paper describes a new approach to low-phasenoise LC VCO design based on
transconductance linearization of the active devices. A prototype 25 GHz VCO based on this …
transconductance linearization of the active devices. A prototype 25 GHz VCO based on this …
A low phase noise, wideband and compact CMOS PLL for use in a heterodyne 802.15. 3c transceiver
A low phase noise, wideband, mm-wave, integer-N PLL that is capable of supporting an
802.15. 3c heterodyne transceiver is reported. The PLL can generate 6 equally spaced …
802.15. 3c heterodyne transceiver is reported. The PLL can generate 6 equally spaced …
Linear CMOS -VCO Based on Triple-Coupled Inductors and Its Application to 40-GHz Phase-Locked Loop
A linear CMOS voltage-controlled oscillator (VCO) utilizing triple-coupled inductors and a 40-
GHz integer-N phase-locked loop (PLL) are fabricated in a standard 90-nm CMOS process …
GHz integer-N phase-locked loop (PLL) are fabricated in a standard 90-nm CMOS process …
A wideband receiver for multi-Gbit/s communications in 65 nm CMOS
F Vecchi, S Bozzola, E Temporiti… - IEEE Journal of Solid …, 2011 - ieeexplore.ieee.org
High-rate communications technology leveraging the unlicensed spectrum around 60 GHz
is almost ready for deployment with several demonstrations of successful wireless links. One …
is almost ready for deployment with several demonstrations of successful wireless links. One …
A programmable frequency multiplier-by-29 architecture for millimeter wave applications
C Jany, A Siligaris… - IEEE Journal of Solid …, 2015 - ieeexplore.ieee.org
This paper presents an original mmW frequency multiplier that provides the channel center
frequencies of the IEEE 802.15. 3c standard from a much lower and fixed frequency of 2.16 …
frequencies of the IEEE 802.15. 3c standard from a much lower and fixed frequency of 2.16 …
Low-Phase-Noise 20-GHz Phase-Locked Loop Using Harmonic-Tuned VCO Assisting With -Boosting Technique
In this study, we present a low-phase-noise 20-GHz phase-locked loop (PLL) with
simultaneous-boosted and third-harmonic impedance-tuned voltage-controlled oscillator …
simultaneous-boosted and third-harmonic impedance-tuned voltage-controlled oscillator …
A 30-GHz power-efficient PLL frequency synthesizer for 60-GHz applications
N Mahalingam, Y Wang, BK Thangarasu… - IEEE Transactions …, 2017 - ieeexplore.ieee.org
This paper presents the design and verification of a proposed 30-GHz power-efficient phase-
locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a …
locked loop (PLL) frequency synthesizer for 60-GHz applications. Fabricated by a …