In this paper, a procedure for intellectual property protection (IPP) of digital circuits called
IPP@ HDL is presented. Its aim is to protect the author rights in the development and …

Modulo 2/sup n/+ 1 adders find great applicability in several applications including RNS
implementations and cryptography. In this paper, we present two novel architectures for …

Two architectures for modulo 2 n+ 1 adders are introduced in this paper. The first one is built
around a sparse carry computation unit that computes only some of the carries of the modulo …

In the last years, investigation on residue number systems (RNS) has targeted parallelism
and larger dynamic ranges. In this paper, we start from the moduli set {2 n, 2 n-1, 2 n+ 1, 2 n …

A new modulo 2n+ 1 multiplier architecture is proposed for operands in the weighted
representation. A new set of partial products is derived and it is shown that all required …

In this paper, it is shown that every architecture proposed for modulo 2 n+ 1 addition of
operands that follow the diminished-1 representation can also be used in the design of …

This research discusses a novel watermarking scheme using redundant residue number
system and chaos. The salient feature of said research is that image remains fragile while …

The residue number system (RNS) is a carry-free number system which can support high-
speed and parallel arithmetic. Two major issues in efficient design of RNS systems are the …

Residue Number System (RNS) is a modular representation and is proved to be an
instrumental tool in many digital signal processing (DSP) applications which require high …

In recent years, research on residue number systems (RNS) has targeted larger dynamic
ranges to explore their inherent parallelism further. In this paper, we start from the traditional …