Optimal compilation for exposed datapath architectures with buffered processing units by SAT solvers

A Bhagyanath, K Schneider - 2016 ACM/IEEE International …, 2016 - ieeexplore.ieee.org
Conventional processor architectures are restricted in exploiting instruction level parallelism
(ILP) due to the limited number of available registers in their instruction sets. Therefore …

Exploring the potential of instruction-level parallelism of exposed datapath architectures with buffered processing units

A Bhagyanath, K Schneider - 2017 17th International …, 2017 - ieeexplore.ieee.org
Recent processor architectures expose their datapaths to the compiler so that the compiler
not only takes care of scheduling instructions to the available processing units but also of …

Towards buffers as a scalable alternative to registers for processor-local memory

J Roob, A Bhagyanath… - MBMV 2023; 26th …, 2023 - ieeexplore.ieee.org
Processors require local memory close to the execution units to bridge the long latencies for
accessing the comparatively slow main memory. In particular, traditional processor …

[PDF][PDF] Towards code generation for the synchronous control asynchronous dataflow (SCAD) architectures

A Bhagyanath, T Jain, K Schneider - MBMV, 2016 - d-nb.info
Many recent processor architectures expose their datapaths so that the compiler can not
only schedule instructions to increase instruction-level concurrency, but can even take care …

[PDF][PDF] Code generation for synchronous control asynchronous dataflow architectures

A Bhagyanath - 2021 - d-nb.info
Scaling up conventional processor architectures cannot translate the everincreasing number
of transistors into comparable application performance. Although the trend is to shift from …

A vector-length agnostic compiler for the connex-s accelerator with scratchpad memory

AE Şuşu - ACM Transactions on Embedded Computing Systems …, 2020 - dl.acm.org
Compiling sequential C programs for Connex-S, a competitive, scalable and customizable,
wide vector accelerator for intensive embedded applications with 32 to 4,096 16-bit integer …

Nonblocking on-chip interconnection networks

T Jain - 2020 - kluedo.ub.rptu.de
Interconnection networks enable fast data communication between components of a digital
system. The selection of an appropriate interconnection network and its architecture plays …

A configurable SIMD architecture with explicit datapath for intelligent learning

Y He, M Peemen, L Waeijen, E Diken… - 2016 International …, 2016 - ieeexplore.ieee.org
The use of a wide Single-Instruction-Multiple-Data (SIMD) architecture is a promising
approach to build energy-efficient high performance embedded processors. In this paper …

R-Blocks: an Energy-Efficient, Flexible, and Programmable CGRA

B de Bruin, K Vadivel, M Wijtvliet… - ACM Transactions on …, 2024 - dl.acm.org
Emerging data-driven applications in the embedded, e-Health, and internet of things (IoT)
domain require complex on-device signal analysis and data reduction to maximize energy …

Code generation for reconfigurable explicit datapath architectures with llvm

M Adriaansen, M Wijtvliet, R Jordans… - … on Digital System …, 2016 - ieeexplore.ieee.org
Good tool support is essential for computing platforms because they increase the
programmability of the platform. This is especially the case for reconfigurable architectures …