Photon-number-resolving megapixel image sensor at room temperature without avalanche gain
In several emerging fields of study such as encryption in optical communications,
determination of the number of photons in an optical pulse is of great importance. Typically …
determination of the number of photons in an optical pulse is of great importance. Typically …
Full-color nanorouter for high-resolution imaging
Pixel scaling effects have been a major issue in the development of high-resolution color
image sensors due to the reduced photoelectric signal and color crosstalk. Various structural …
image sensors due to the reduced photoelectric signal and color crosstalk. Various structural …
[PDF][PDF] Pixel-to-pixel isolation by deep trench technology: application to CMOS image sensor
A Tournier, F Leverd, L Favennec… - Proc. Int. image …, 2011 - imagesensors.org
Deep Trench technology for CMOS image sensor was successfully developed and
industrialized for bestin-class 1.4 µm pixel Front-Side Illumination (FSI) technology. The …
industrialized for bestin-class 1.4 µm pixel Front-Side Illumination (FSI) technology. The …
Surrounding gate transistor (SGT) structure
F Masuoka, H Nakamura, S Arai, T Kudo… - US Patent …, 2015 - Google Patents
2011-05-26 Assigned to UNISANTIS ELECTRONICS (JAPAN) LTD. reassignment
UNISANTIS ELECTRONICS (JAPAN) LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE …
UNISANTIS ELECTRONICS (JAPAN) LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE …
Semiconductor device including a MOS transistor and production method therefor
F Masuoka, S Arai - US Patent 8,497,548, 2013 - Google Patents
It is intended to provide a semiconductor device including a MOS transistor, comprising: a
semiconductor pillar; a bottom doped region formed in contact with a lower part of the …
semiconductor pillar; a bottom doped region formed in contact with a lower part of the …
Semiconductor device and production method therefor
F Masuoka, S Arai - US Patent 8,598,650, 2013 - Google Patents
It is intended to provide a semiconductor device comprising a circuit which has a connection
between a drain region or a source region of a first MOS transistor and a drain region ora …
between a drain region or a source region of a first MOS transistor and a drain region ora …
Surround gate CMOS semiconductor device
F Masuoka, H Nakamura, S Arai, T Kudo… - US Patent …, 2013 - Google Patents
2011-05-23 Assigned to UNISANTIS ELECTRONICS (JAPAN) LTD. reassignment
UNISANTIS ELECTRONICS (JAPAN) LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE …
UNISANTIS ELECTRONICS (JAPAN) LTD. ASSIGNMENT OF ASSIGNORS INTEREST (SEE …
A 45 nm stacked CMOS image sensor process technology for submicron pixel
S Takahashi, YM Huang, JJ Sze, TT Wu, FS Guo… - Sensors, 2017 - mdpi.com
A submicron pixel's light and dark performance were studied by experiment and simulation.
An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is …
An advanced node technology incorporated with a stacked CMOS image sensor (CIS) is …
A 368× 184 optical under-display fingerprint sensor comprising hybrid arrays of global and rolling shutter pixels with shared pixel-level ADCs
PH Yin, CW Lu, JS Wang, KL Chang… - IEEE Journal of Solid …, 2021 - ieeexplore.ieee.org
This study proposes a 368 x 184 optical underdisplay fingerprint sensor designed and
prototyped using the 0.11-μm CIS technology. The prototype sensor includes a hybrid array …
prototyped using the 0.11-μm CIS technology. The prototype sensor includes a hybrid array …
High-resolution CMOS video image sensors
I Takayanagi, J Nakamura - Proceedings of the IEEE, 2012 - ieeexplore.ieee.org
High-definition television (HDTV) images are now commonly available and the recent trend
of video applications is toward even higher spatial resolutions with higher pixel rates. To …
of video applications is toward even higher spatial resolutions with higher pixel rates. To …