Insulated gate and surface passivation structures for GaN-based power transistors
Recent years have witnessed GaN-based devices delivering their promise of
unprecedented power and frequency levels and demonstrating their capability as an able …
unprecedented power and frequency levels and demonstrating their capability as an able …
[HTML][HTML] Controlling surface/interface states in GaN-based transistors: Surface model, insulated gate, and surface passivation
Controlling surface/interface states in GaN-based transistors: Surface model, insulated gate,
and surface passivation | Journal of Applied Physics | AIP Publishing Skip to Main Content …
and surface passivation | Journal of Applied Physics | AIP Publishing Skip to Main Content …
Border traps in Ge/III–V channel devices: Analysis and reliability aspects
The aim of this review paper is to describe the impact of so-called border traps (BTs) in high-
k gate oxides on the operation and reliability of high-mobility channel transistors. First, a …
k gate oxides on the operation and reliability of high-mobility channel transistors. First, a …
Total-Ionizing-Dose Effects, Border Traps, and 1/f Noise in Emerging MOS Technologies
DM Fleetwood - IEEE Transactions on Nuclear Science, 2020 - ieeexplore.ieee.org
Subthreshold leakage currents and threshold-voltage shifts due to total-ionizing-dose (TID)
irradiation are reviewed briefly for highly scaled devices in emerging MOS technologies …
irradiation are reviewed briefly for highly scaled devices in emerging MOS technologies …
A Distributed Bulk-Oxide Trap Model for InGaAs MOS Devices
Y Yuan, B Yu, J Ahn, PC McIntyre… - … on Electron Devices, 2012 - ieeexplore.ieee.org
This paper presents a distributed circuit model for bulk-oxide traps based on tunneling
between the semiconductor surface and trap states in the gate dielectric film. The model is …
between the semiconductor surface and trap states in the gate dielectric film. The model is …
Border traps and bias-temperature instabilities in MOS devices
DM Fleetwood - Microelectronics Reliability, 2018 - Elsevier
An overview of the effects of border traps on device performance and reliability is presented
for Si, Ge, SiGe, InGaAs, SiC, GaN, and carbon-based MOS devices that are subjected to …
for Si, Ge, SiGe, InGaAs, SiC, GaN, and carbon-based MOS devices that are subjected to …
Evaluation of border traps and interface traps in HfO2/MoS2 gate stacks by capacitance–voltage analysis
Border traps and interface traps in HfO 2/few-layer MoS 2 top-gate stacks are investigated by
C–V characterization. Frequency dependent C–V data shows dispersion in both the …
C–V characterization. Frequency dependent C–V data shows dispersion in both the …
Defect state passivation at III-V oxide interfaces for complementary metal–oxide–semiconductor devices
J Robertson, Y Guo, L Lin - Journal of Applied Physics, 2015 - pubs.aip.org
The paper describes the reasons for the greater difficulty in the passivation of interface
defects of III–V semiconductors like GaAs. These include the more complex reconstructions …
defects of III–V semiconductors like GaAs. These include the more complex reconstructions …
New method for determining flat-band voltage in high mobility semiconductors
The method that is commonly used for determining the flat-band voltage (V FB) and the flat-
band capacitance (C FB) of metal oxide semiconductor (MOS) capacitors depends on many …
band capacitance (C FB) of metal oxide semiconductor (MOS) capacitors depends on many …
Characterization of Al Incorporation into HfO2 Dielectric by Atomic Layer Deposition
This study presents the characteristics of HfAlO films for a series of Al incorporation ratios
into a HfO2 dielectric by atomic layer deposition on a Si substrate. A small amount of Al …
into a HfO2 dielectric by atomic layer deposition on a Si substrate. A small amount of Al …